# US 2013/0278239 A1 · Precharge circuits and methods for dc-dc boost converters > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0278239 A1 - Document ID: US20130278239A1 - Status: Published application - Kind: A1 - Application number: 13/849,623 - Filed: 2013-03-25 - Published: 2013-10-24 - Earliest claimed: 2012-04-20 - Assignees: Silergy Semiconductor Technology (Hangzhou) LTD - Applicants: Silergy Semiconductor Technology (Hangzhou) Ltd - Inventors: Jinping Dong - Web page: https://patentgrep.com/patent/US20130278239A1 ## CPC - H02M 1/36: Means for starting or stopping converters - H02M 3/156: with automatic control of output voltage or current, e.g. switching regulators - H02M 3/157: with digital control - H02M 3/158: including plural semiconductor devices as final control devices for a single load - G05F 3/26: Current mirrors - H02M 1/0045: {Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode} - H02M 3/155: using semiconductor devices only - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract The present invention discloses precharge circuits and methods for DC-DC boost converters. In one embodiment, a precharge method for a DC-DC boost converter having a current mirror circuit that includes a reference transistor and a power transistor, can include: (i) maintaining a reference current flowing through the reference transistor as substantially constant; (ii) maintaining a drain-source voltage of the reference transistor and a drain-source voltage of the power transistor as substantially equal; and (iii) obtaining a substantially constant mirror current by reflecting the reference current through the power transistor to operate as a precharging current of a precharge circuit. ## Claims ### Claim 1 A precharge method for a DC-DC boost converter comprising a current mirror circuit having a reference transistor and a power transistor, the method comprising: a) maintaining a reference current flowing through said reference transistor as substantially constant; b) maintaining a drain-source voltage of said reference transistor and a drain-source voltage of said power transistor as substantially equal; and c) obtaining a substantially constant mirror current by reflecting said reference current through said power transistor to operate as a precharging current of a precharge circuit. ### Claim 2 (depends on 1) The method of claim 1, wherein said maintaining said reference current flowing through said reference transistor as substantially constant comprises: a) increasing a gate-source voltage of said reference transistor when said reference current is decreasing, to increase said reference current; and b) reducing said gate-source voltage of said reference transistor when said reference current is increasing, to lower said reference current. ### Claim 3 (depends on 1) The method of claim 1, wherein said maintaining said drain-source voltage of said reference transistor and said drain-source voltage of said power transistor as substantially equal comprises controlling a drain voltage of said reference transistor to follow a drain voltage variation of said power transistor. ### Claim 4 A precharge circuit configured with a DC-DC boost converter, the precharge circuit comprising: a) a current mirror circuit having a reference transistor and a power transistor; b) a voltage clamping circuit coupled to said current mirror circuit, wherein said voltage clamping circuit is configured to maintain drain-source voltages of said reference transistor and said power transistor as substantially equal; and c) a current regulating circuit coupled to said current mirror circuit and said voltage clamping circuit, wherein said current regulating circuit is configured to compare a voltage from said voltage clamping circuit against a reference voltage, and to control in response thereto regulation of a reference current and a precharging current of said precharge circuit as substantially constant. ### Claim 5 (depends on 4) The precharge circuit of claim 4, wherein said voltage from said voltage clamping circuit that is compared against said reference voltage is configured to represent a current through said reference transistor. ### Claim 6 (depends on 4) The precharge circuit of claim 4, wherein a drain voltage of said reference transistor is configured to be clamped by said voltage clamping circuit to maintain said drain voltage of said reference transistor and a drain voltage of said power transistor as substantially equal. ### Claim 7 (depends on 4) The precharge circuit of claim 4, wherein said reference voltage is configured to be regulated according to a load of said DC-DC boost converter. ### Claim 8 (depends on 4) The precharge circuit of claim 4, wherein said voltage clamping circuit comprises: a) a first transistor coupled to said reference transistor and a sampling circuit; and b) a second transistor coupled to said power transistor and a current-stabilizer circuit, wherein gates of said first and second transistors are coupled together and to a drain of said second transistor. ### Claim 9 (depends on 8) The precharge circuit of claim 8, wherein said current regulating circuit comprises an error amplifier having: a) a non-inverting input terminal coupled to a common junction of said first transistor and said sampling circuit; b) an inverting input terminal coupled to said reference voltage; and c) an output terminal coupled to gates of said reference transistor and said power transistor. ### Claim 10 (depends on 9) The precharge circuit of claim 9, wherein: a) a voltage at said common junction is configured to represent said reference current flowing through said reference transistor; b) said error amplifier is configured to output a negative error voltage signal to increase said reference current when said common junction voltage is less than said reference voltage; and c) said error amplifier is configured to output a positive error voltage signal to reduce said reference current when said common junction voltage is greater than said reference voltage.