# US 2013/0277828 A1 · Methods and Apparatus for bump-on-trace Chip Packaging

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- Number: US 2013/0277828 A1
- Document ID: US20130277828A1
- Status: Published application
- Kind: A1
- Application number: 13/450,191
- Filed: 2012-04-18
- Published: 2013-10-24
- Earliest claimed: 2012-04-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chang-Chia Huang; Tsung-Shu Lin; Han-Ping Pu; Yen-Liang Lin; Sheng-Hsiang Chiu
- Web page: https://patentgrep.com/patent/US20130277828A1

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/687: {characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage}
- H10W 72/072: {of bump connectors}
- H10W 72/07211: {Treating the bond pad before connecting, e.g. by applying flux or cleaning}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/354: {comprising polymers}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods and apparatus for a solder mask trench used in a bump-on-trace (BOT) structure to form a semiconductor package are disclosed. A solder mask layer is formed on a trace and on a substrate. An opening of the solder mask layer, called a solder mask trench, is formed to expose the trace on the substrate. The solder mask trench has a width about a size of a diameter of a solder bump. A solder bump is landed directly on the exposed trace to connect a chip to the trace by an interconnect. With the formation of the solder mask trench, the trace exposed in the solder mask trench have a better grab force, which reduces the trace peeling failure for the semiconductor package. A plurality of solder mask trench rings may be formed in a package.

## Claims

### Claim 1

A device comprising:
a substrate;
a trace on the substrate,
a solder mask layer on the substrate and on the trace, wherein the solder mask layer has a solder mask trench to expose the trace, and the solder mask trench has a width about a size of a diameter of a solder bump; and
a solder bump landed directly on the trace exposed by the solder mask trench wherein the solder bump is a part of an interconnect of a chip.

### Claim 2 (depends on 1)

The device of claim 1, further comprising a chip connected to the interconnect.

### Claim 3 (depends on 2)

The device of claim 2, further comprising an under-fill material filling a gap between the chip and the substrate.

### Claim 4 (depends on 1)

The device of claim 1, wherein the substrate is made of a laminate or an organic material.

### Claim 5 (depends on 1)

The device of claim 1, wherein the solder mask layer is about 30 to 40 microns in height.

### Claim 6 (depends on 1)

The device of claim 1, wherein the trace comprises a material selected from a group consisting essentially of pure copper, aluminum copper, or alloys.

### Claim 7 (depends on 1)

The device of claim 1, wherein the trace has a trace body that is of a substantially constant thickness.

### Claim 8 (depends on 1)

The device of claim 1, wherein the interconnect is of a shape of a circle, an octagon, a rectangle, an oval, or a diamond.

### Claim 9 (depends on 1)

The device of claim 1, wherein the interconnect comprises a post and the solder bump.

### Claim 10 (depends on 1)

The device of claim 1, wherein the solder bump comprises a material selected from a group consisting essentially of tin, silver, lead-free tin, copper, or a combination thereof.

### Claim at position 11

-17. (canceled)

### Claim 18

A semiconductor package, comprising:
a substrate with a plurality of traces;
a solder mask layer on the substrate and the plurality of traces;
a trench in the solder mask layer to expose portions of the plurality of traces; and
at least one solder bump landed directly on at least one of the exposed plurality of traces, wherein the solder bump is a part of an interconnect of a chip.

### Claim 19 (depends on 18)

The package of claim 18, wherein a pitch between two interconnects is less than about 140 um.

### Claim 20 (depends on 1)

The device of claim 1, wherein the trace has a trace body that is of a substantially constant thickness.

### Claim 21

A device comprising:
a trace on a substrate,
a solder mask layer on the trace, wherein the solder mask layer has a solder mask trench to expose the trace, and the solder mask trench has a width about a size of a diameter of a connector; and
the connector landed on the trace exposed by the solder mask trench wherein the connector is a part of an interconnect of a chip.

### Claim 22 (depends on 21)

The device of claim 21, further comprising a chip connected to the interconnect.

### Claim 23 (depends on 21)

The device of claim 21, wherein the solder mask layer is about 30 to 40 microns in height.

### Claim 24 (depends on 21)

The device of claim 21, wherein the trace comprises a material selected from a group consisting essentially of pure copper, aluminum copper, or alloys.

### Claim 25 (depends on 21)

The device of claim 21, wherein the trace has a trace body that is of a substantially constant thickness.

### Claim 26 (depends on 21)

The device of claim 21, wherein the interconnect is of a shape of a circle, an octagon, a rectangle, an oval, or a diamond.

### Claim 27 (depends on 21)

The device of claim 21, wherein the interconnect comprises a post and a solder bump.