# US 2013/0277779 A1 · Method and structure of sensors or electronic devices using vertical mounting

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- Number: US 2013/0277779 A1
- Document ID: US20130277779A1
- Status: Published application
- Kind: A1
- Application number: 13/922,983
- Filed: 2013-06-20
- Published: 2013-10-24
- Earliest claimed: 2010-05-24
- Assignees: MCube Inc. (028143)
- Applicants: MCube Inc. (028143)
- Inventors: Xiao(Charles) Yang; Hong Wan
- Web page: https://patentgrep.com/patent/US20130277779A1

## CPC

- H10W 90/00: Package configurations
- B81B 7/007: {Interconnections between the MEMS and external electrical signals}
- B81B 7/0074: {3D packaging, i.e. encapsulation containing one or several MEMS devices arranged in planes non-parallel to the mounting board}
- H10W 72/019: {of bond pads}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 72/0198: {batch processes}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 74/014: {using batch processing}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00)

## Abstract

A method and structure for fabricating sensor(s) or electronic device(s) using vertical mounting is presented. The method includes providing a substrate having a surface region and forming sensor(s) or electronic device(s) on a first region overlying the surface region. At least one bond pad structure can be formed from at least one trench structure. The resulting device can then be singulated within a vicinity of the bond pad structure(s) to form at least one integrated sensor or electronic devices having at least one vertical bond pad. At least one singulated device(s) can be coupled to a package, having a package surface region, such that the vertical bond pad(s) are configured horizontally, and at least one interconnection can be formed between the vertical bond pad(s) and at least one portion of the package surface region.

## Claims

### Claim 1

An integrated system, the system comprising:
a substrate having a surface region;
at least one integrated device formed on a first region overlying the surface region, the at least one integrated device having at least one contact region, the first region having a first surface region, the at least one integrated device including one or more sensors and/or one or more electronic devices;
at least one trench structure formed within at least one portion of the first region;
a dielectric material formed overlying the first region and the at least one trench structure, the dielectric material having at least one portion removed within a vicinity of the at least one contact region;
a conduction material formed overlying the dielectric material, the at least one trench structure, and the at least one contact region, the conduction material having at least one portion removed within a vicinity of the at least one contact region and the at least one trench structure to form at least one bonding structure, the resulting device being singulated within a vicinity of the at least one bonding structure to form at least one singulated integrated device having at least one vertical bond pad;
a package coupled to at least one singulated integrated device, the package having a package surface region, the at least one singulated device being coupled to the package surface region such that the at least one vertical bond pad are configured horizontally; and
at least one interconnection formed between the at least one vertical bond pad and at least a portion of the package surface region.

### Claim 2 (depends on 1)

The system of claim 1 wherein the at least one integrated device comprises a nickel-iron material.

### Claim 3 (depends on 1)

The system of claim 1 wherein the electronic devices comprise CMOS integrated circuit devices.

### Claim 4 (depends on 1)

The system of claim 1 wherein the sensors comprise MEMS devices.

### Claim 5 (depends on 1)

The system of claim 1 wherein the sensors comprise magnetoresistance devices.

### Claim 6 (depends on 5)

The system of claim 5 wherein the magnetoresistance devices comprise anisotropic magnetoresistance (AMR), ordinary magnetoresistance (OMR), giant magnetoresistance (GMR), or tunnel junction magnetoresistance (TMR) devices.

### Claim 7 (depends on 1)

The system of claim 1 wherein the at least one trench structure is formed from a wet etching, dry etching, deep reactive-ion etching (DRIE), or mechanical process.

### Claim 8 (depends on 1)

The system of claim 1 wherein the removing of at least one portion of the dielectric material and the removing of at least one portion of the conduction material comprise a wet etching, dry etching, or mechanical process.

### Claim 9 (depends on 1)

The system of claim 1 wherein the singulating of the resulting device comprises a dicing, an etching, or a laser scribing process.

### Claim 10 (depends on 1)

The system of claim 1 wherein the package is a substrate package or a lead frame package.

### Claim 11 (depends on 1)

The system of claim 1 wherein the at least one interconnection is formed via a wire bonding process.