Non-Planar Transistors and Methods of Fabrication Thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Hang Tung, Chin-Hsiang Lin, Cheng-Hung Chang, Sey-Ping Sun
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Abstract
Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region.
Claims20
A non-planar transistor comprising:
- a fin comprising a top surface and sidewalls, the fin comprising a first portion, a second portion, and a third portion disposed between the first and the second portion;
- a dopant rich semiconductor layer disposed on the first and the second portions of the fin, the dopant rich semiconductor layer comprising a first conductivity type, wherein the dopant rich semiconductor layer comprises a uniform thickness along a direction parallel to the sidewalls of the fin;
- a channel region disposed on the third portion of the fin and comprising an opposite second conductivity type;
- and
- a silicide layer disposed on a top surface and sidewalls of the dopant rich semiconductor layer, wherein the silicide layer is adjacent to the dopant rich layer.
A device comprising:
- a channel region on a first portion of a semiconductor fin, the semiconductor fin comprising a top surface and sidewalls;
- a gate electrode over the channel region of the semiconductor fin;
- a doped semiconductor layer of a first material disposed on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode and having a first doping profile and a first doping concentration;
- a silicide layer contacting the doped semiconductor layer, the silicide layer comprising a silicide metal and the first material;
- and
- a dopant rich region disposed in the doped semiconductor layer and abutting the silicide layer.
A device comprising:
- a channel region on a first portion of a semiconductor fin, the semiconductor fin comprising a top surface and sidewalls;
- a gate electrode over the channel region of the semiconductor fin;
- an epitaxial semiconductor layer on the top surface and the sidewalls of a portion of the semiconductor fin on opposing sides of the date electrode, the semiconductor layer having a first doping profile;
- an epitaxial doped semiconductor layer having a second doping profile over the epitaxial semiconductor layer, the first doping profile different than the second doping profile;
- a silicide layer over the doped semiconductor layer;
- and
- a dopant rich layer having a uniform thickness disposed in the doped semiconductor layer, the dopant rich layer adjacent to the silicide layer.
Dependencies are inferred from the claim text.