# US 2013/0277686 A1 · Semiconductor Structure with Metal Gate and Method of Fabricating the Same

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- Number: US 2013/0277686 A1
- Document ID: US20130277686A1
- Status: Published application
- Kind: A1
- Application number: 13/454,036
- Filed: 2012-04-23
- Published: 2013-10-24
- Earliest claimed: 2012-04-23
- Assignees: United Microelectronics Corp.
- Inventors: An-Chi Liu; Chun-Hsien Lin
- Web page: https://patentgrep.com/patent/US20130277686A1

## CPC

- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A metal gate process comprises the steps of providing a substrate, forming a dummy gate on said substrate, forming dummy spacers on at least one of the surrounding sidewalls of said dummy gate, forming a source and a drain respectively in said substrate at both sides of said dummy gate, performing a replacement metal gate process to replace said dummy gate with a metal gate, removing said dummy spacers, and forming low-K spacers to replace said dummy spacers.

## Claims

### Claim 1

A fin field effect transistor (Fin FET) process, comprising the step of:
providing a substrate;
forming at least one fin structures on said substrates;
forming a dummy gate on part of said fin structure;
forming dummy spacers on at least one of the surrounding sidewalls of said dummy gate;
forming a source and a drain respectively in said fin structure at both sides of said dummy gate;
performing a replacement metal gate process to replace said dummy gate with a metal gate;
removing said dummy spacers; and
forming low-K spacers to replace said dummy spacers.

### Claim 2 (depends on 1)

The fin field effect transistor process according to claim 1, wherein said replacement metal gate process is performed before removing said dummy spacers.

### Claim 3 (depends on 1)

The fin field effect transistor process according to claim 1, wherein said replacement metal gate process is performed after forming said low-K spacers.

### Claim 4 (depends on 1)

The fin field effect transistor process according to claim 1, wherein said low-K spacer is formed by spin-on-glass (SOG) process.

### Claim 5 (depends on 4)

The fin field effect transistor process according to claim 4, wherein the step of forming said low-K spacer comprises introducing the precursor, such as hydrogen polysilozane, methyl silsesquioxane, or organo aromatic polymer.

### Claim 6 (depends on 1)

The fin field effect transistor process according to claim 1, further comprising the step of forming a liner layer on the sidewall of said dummy gate before forming said dummy spacer, wherein the material of said liner layer comprises silicon carbonitride (SiCN), silicon oxynitride (SiON), and silicon nitride (SiN).

### Claim 7 (depends on 1)

The fin field effect transistor process according to claim 1, further comprising the step of forming a liner layer on the sidewall of said metal gate before forming said low-K spacers, wherein the material of said liner layer comprises silicon carbonitride (SiCN), silicon oxynitride (SiON), and silicon nitride (SiN).

### Claim 8 (depends on 1)

The fin field effect transistor process according to claim 1, further comprising the step of forming a liner layer before forming said dummy spacers or before forming said low-K spacers, wherein the material of said liner layer comprises silicon carbonitride (SiCN), silicon oxynitride (SiON), and silicon nitride (SiN).

### Claim 9 (depends on 1)

The fin field effect transistor process according to claim 1, wherein the material of said dummy spacers comprises silicon nitride (SiN) or advanced pattern film (APF).

### Claim 10 (depends on 1)

The fin field effect transistor process according to claim 1, further comprising the step of forming a lightly doped drain (LDD) in said fin structure before forming said low-K spacer.

### Claim 11 (depends on 1)

The fin field effect transistor process according to claim 1, further comprising the step of forming an epitaxial structure respectively on/in said fin structure at both sides of said dummy gate.

### Claim 12 (depends on 11)

The fin field effect transistor process according to claim 11, wherein the material of said epitaxial structure comprises Si—Ge epitaxy or Si—C epitaxy.

### Claim 13

A semiconductor structure with metal gate, comprising:
a substrate;
a metal gate on said substrate;
epitaxial structures disposed respectively at both sides of said metal gate; and
low-K spacers disposed respectively in the recesses between said metal gate and said epitaxial structures, and the top surface of said low-K spacers are lower than the top surface of said metal gate.

### Claim 14 (depends on 13)

The semiconductor structure with metal gate according to claim 13, further comprising a liner layer formed on the surface of said recess between said metal gate and said epitaxial structure, and said liner layer surrounds said low-K spacer.

### Claim 15 (depends on 14)

The semiconductor structure with metal gate according to claim 14, wherein the material of said liner layer comprises silicon carbonitride (SiCN), silicon oxynitride (SiON), and silicon nitride (SiN).

### Claim 16 (depends on 13)

The semiconductor structure with metal gate according to claim 13, wherein said epitaxial structure comprises a source and a drain.

### Claim 17 (depends on 13)

The semiconductor structure with metal gate according to claim 13, the material of said epitaxial structure comprises Si—Ge epitaxy or Si—C epitaxy.

### Claim 18

A fin field effect transistor (Fin FET), comprising:
a substrate;
at least one fin structures formed on said substrate;
a gate formed on said fin structure;
epitaxial structures formed respectively in said fin structure at both sides of said gate; and
low-K spacers formed respectively in the recesses between said gate and said epitaxial structures and in the recesses surrounding said fin structures, wherein said low-K spacers are leveled with the top surface of said epitaxial structures and lower than the top surface of said gate.

### Claim 19 (depends on 18)

The fin field effect transistor according to claim 18, further comprising a liner layer formed between said gate and said epitaxial structure.

### Claim 20 (depends on 19)

The fin field effect transistor according to claim 19, wherein the material of said liner layer comprises silicon carbonitride (SiCN), silicon oxynitride (SiON), and silicon nitride (SiN).

### Claim 21 (depends on 18)

The fin field effect transistor according to claim 18, wherein said epitaxial structure comprises a source and a drain.

### Claim 22 (depends on 18)

The fin field effect transistor according to claim 18, wherein the material of said epitaxial structure comprises Si—Ge epitaxy or Si—C epitaxy.

### Claim 23 (depends on 18)

The fin field effect transistor according to claim 18, wherein said gate comprises a poly-Si gate or a metal gate.