# US 2013/0277635 A1 · Semiconductor device and its manufacturing method

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- Number: US 2013/0277635 A1
- Document ID: US20130277635A1
- Status: Published application
- Kind: A1
- Application number: 13/927,073
- Filed: 2013-06-25
- Published: 2013-10-24
- Earliest claimed: 2010-02-08
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Satoru HANZAWA; Fumihiko NITTA; Nozomu MATSUZAKI; Toshihiro TANAKA
- Web page: https://patentgrep.com/patent/US20130277635A1

## CPC

- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/003: {Cell access}
- G11C 13/0069: {Writing or programming circuits or methods}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/882: {Compounds of sulfur, selenium or tellurium, e.g. chalcogenides}
- G11C 2213/74: Array wherein each memory cell has more than one access device
- G11C 2213/79: Array wherein the access device being a transistor
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

## Claims

### Claim at position 1

1-12. (canceled)

### Claim 13

A semiconductor device comprising:
a plurality of first wirings extending along a first direction;
a plurality of second wirings extending along a second direction which is perpendicular to the first direction; and
a plurality of non-volatile memory cells arranged at intersection points of the first wirings and the second wirings,
wherein each of the non-volatile memory cells includes a resistive storage element and two select transistors, and
wherein, in the first direction, a most outer non-volatile memory cell of the non-volatile memory cells is a buffer cell which does not have a function to read and write data.

### Claim 14 (depends on 13)

A semiconductor device according to the claim 13, wherein:
the resistive storage elements of the non-volatile memory cells except the most outer non-volatile memory cell are connected to the first wirings through first plugs formed under the first wirings,
no first plug is formed over the resistive storage element of the most outer non-volatile memory cell, and
the resistive storage element of the most outer non-volatile memory cell is not connected to any of the first wirings.

### Claim 15 (depends on 14)

A semiconductor device according to the claim 14, wherein:
a plurality of second plugs are formed over impurity regions of the select transistors and under the resistive storage elements of the non-volatile memory cells, and
the resistive storage elements of the non-volatile memory cells are connected to the impurity regions through the second plugs.

### Claim 16 (depends on 15)

A semiconductor device according to the claim 15,
wherein the resistive storage element of each of the non-volatile memory cells includes a chalcogenide film.

### Claim 17 (depends on 13)

A semiconductor device according to the claim 13,
wherein the resistive storage element of each of the non-volatile memory cells includes a chalcogenide film.