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US 2013/0273692 A1Published application
Leadless array plastic package with various ic packaging configurations
AssigneeUTAC Hong Kong Limited
InventorsJohn MCMILLAN, Serafin P. PEDRON, JR., Kirk POWELL, Adonis FUNG
Life of this patent
Estimating the term…
Abstract
A leadless integrated circuit (IC) package comprising an IC chip mounted to a die-attach area and a plurality of electrical contacts electrically connected to the IC chip. The IC chip, the electrical contacts, and the die-attach area are all covered with a molding material, with portions of the electrical contacts and die-attach area protruding from a bottom surface of the molding material.
Claims20
A method of manufacturing a leadless integrated circuit (IC) package comprising:
- providing a leadframe strip having top and bottom surfaces;
- removing portions of the top surface of the leadframe strip to form recesses therein partially defining upper portions of one or more die-attach areas and upper portions of a plurality of electrical contacts;
- mounting a first IC chip to the leadframe strip in a first die-attach area of the partially defined one or more die-attach areas;
- mounting a second IC chip in a second die-attach area of the partially defined one or more die-attach areas;
- forming electrical connections between the plurality of partially defined electrical contacts and the first IC chip;
- covering the first IC chip, the second IC chip, the partially defined one or more die-attach areas, the partially defined electrical contacts, and the electrical connections with a molding layer, the molding layer filling the recesses;
- forming an etch-resist layer on the bottom surface of the leadframe strip corresponding to the partially defined one or more die-attach areas and the plurality of partially defined electrical contacts;
- and
- selectively etching the bottom surface of the leadframe strip using the etch-resist layer as an etching mask, thereby etching through portions of the leadframe strip to define lower portions of the plurality of electrical contacts and lower portions of the one or more die-attach areas.
6 more elements
A method of manufacturing a leadless integrated circuit (IC) package comprising:
- providing a leadframe strip having top and bottom surfaces;
- removing portions of the top surface of the leadframe strip to form recesses therein partially defining an upper portion of a die-attach area and an upper portion of a plurality of electrical contacts;
- mounting an IC chip assembly to the leadframe strip in the partially defined die-attach area, the IC chip assembly comprising a first die and a second die mounted on a top surface thereof in a stacked configuration;
- forming electrical connections between the plurality of partially defined electrical contacts and the IC chip assembly;
- covering the IC chip assembly, the partially defined die-attach area, the partially defined electrical contacts, and the electrical connections with a molding layer, the molding layer filling the recesses;
- forming an etch-resist layer on the bottom surface of the leadframe strip corresponding to the partially defined die-attach area and the plurality of partially defined electrical contacts;
- and
- selectively etching the bottom surface of the leadframe strip using the etch-resist layer as an etching mask, thereby etching through portions of the leadframe strip to define lower portions of the plurality of electrical contacts and a lower portion of the die-attach area.
5 more elements
A method of manufacturing a leadless integrated circuit (IC) package comprising:
- providing a leadframe strip having top and bottom surfaces;
- removing portions of the top surface of the leadframe strip to form recesses therein partially defining upper portions of first and second die-attach areas and upper portions of a plurality of electrical contacts;
- mounting a first IC chip to the leadframe strip in the first partially defined die-attach area;
- mounting a second IC chip to the leadframe strip in the second partially defined die-attach area;
- forming electrical connections between the electrical contacts and the first and second IC chips;
- covering the first and second IC chips, the first and second partially defined die-attach areas, the plurality of partially defined electrical contacts, and the electrical connections with a molding layer, the molding layer filling the recesses;
- forming an etch-resist layer on the bottom surface of the leadframe strip corresponding to the first and second partially defined die-attach areas and the plurality of partially defined electrical contacts;
- and
- selectively etching the bottom surface of the leadframe strip using the etch-resist layer as an etching mask, thereby etching through portions of the leadframe strip to define lower portions of the plurality of electrical contacts and the first and second die-attach areas.
6 more elements
Dependencies are inferred from the claim text.