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US 2013/0270652 A1Published application
Apparatus for FinFETs
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon-Jhy Liaw
Life of this patent
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Abstract
A FinFET comprises an isolation region formed in a substrate, a reverse T-shaped fin formed in the substrate, wherein a bottom portion of the reverse T-shaped fin is enclosed by the isolation region and an upper portion of the reverse T-shaped fin protrudes above a top surface of the isolation region. The FinFET further comprises a gate electrode wrapping the reverse T-shaped fin.
Claims20
An apparatus comprising:
- an isolation region formed in a substrate;
- a reverse T-shaped fin formed in the substrate, wherein:
- a bottom portion of the reverse T-shaped fin is enclosed by the isolation region;
- and
- an upper portion of the reverse T-shaped fin protrudes above a top surface of the isolation region, and wherein the reverse T-shaped fin comprises:
- a channel connected between a first drain/source region and a second drain/source region;
- and
- a gate electrode wrapping the channel of the reverse T-shaped fin.
5 more elements
A device comprising:
- an isolation region formed in a substrate;
- a first fin structure comprising:
- a first two-stage fin formed in the substrate, wherein:
- a bottom portion of first two-stage fin is enclosed by the isolation region;
- and
- an upper portion of the first two-stage fin protrudes above a top surface of the isolation region, and wherein the first two-stage fin comprises:
- a first channel connected between a first drain/source region and a second drain/source region;
- and
- a first gate electrode wrapping the first channel of the first two-stage fin;
- and
- a second fin structure comprising:
- a second two-stage fin formed in the substrate, wherein:
- a bottom portion of second two-stage fin is enclosed by the isolation region;
- and
- an upper portion of the second two-stage fin protrudes above a top surface of the isolation region, and wherein the second two-stage fin comprises:
- a second channel connected between a third drain/source region and a fourth drain/source region;
- and
- a second gate electrode wrapping the second channel of the second two-stage fin.
15 more elements
A memory cell comprising:
- a first inverter comprising:
- a first p-type transistor (PU) having a two-stage fin structure;
- and
- a first n-type transistor (PD) having the two-stage fin structure, wherein the first PU is connected in series with the first PD;
- a second inverter cross-coupled to the first inverter comprising:
- a second PU having the two-stage fin structure;
- and
- a second PD having the two-stage fin structure, wherein the second PU is connected in series with the second PD;
- a first pass-gate transistor having the two-stage fin structure, wherein the first pass-gate transistor is coupled between the first inverter and a first bit line;
- and
- a second pass-gate transistor having the two-stage fin structure, wherein the second pass-gate transistor is coupled between the second inverter and a second bit line.
8 more elements
Dependencies are inferred from the claim text.