Staggered column superjunction

A method of manufacturing a staggered column vertical superjunction semiconductor device comprising:

• a) applying a first mask to a surface of a first semiconductor layer of a first conductivity type, wherein the first mask is patterned with openings positioned at locations corresponding to a first column and no openings at locations corresponding to a second column;
• b) implanting dopants having a second conductivity type through the openings to form first implanted regions;
• c) growing a second semiconductor layer of a first conductivity type on top of the first semiconductor layer;
• d) applying a second mask on the surface of the second semiconductor layer, wherein the second mask is patterned with openings positioned at locations corresponding to the first and second columns;
• e) implanting the dopants of the second conductivity type through the openings positioned at locations corresponding to the first and second columns to form the second implanted regions;
• and
• f) repeating steps c) through f) to form first and second columns of the second conductivity type in a cumulative semiconductor layer of first conductivity type, whereby a cumulative semiconductor layer comprises the first semiconductor layer and one or more subsequent semiconductor layers grown on top of it, and wherein at least some of the first columns are located in a active cell region.