Maximum-likelihood decoder in a memory controller for synchronization
AssigneeIntel Corporation
InventorRavi Motwani
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Abstract
Described herein are apparatus, system, and method for data synchronization via a maximum-likelihood decoder in a memory controller. The method comprises receiving a constrained codeword from a non-volatile memory (NVM) via a channel, the constrained codeword including an appended bit-stream; and decoding the received constrained codeword by reconstructing the appended bit-stream and invoking a synchronization procedure that applies a maximum-likelihood (ML) estimator to estimate locations of any insertion, deletion, or error in the reconstructed appended bit-stream.
Claims29
A method comprising:
- receiving a constrained codeword from a non-volatile memory (NVM) via a channel, the constrained codeword including an appended bit-stream;
- and
- decoding the received constrained codeword by reconstructing the appended bit-stream and invoking a synchronization procedure that applies a maximum-likelihood (ML) estimator to estimate locations of any insertion, deletion, or error in the reconstructed appended bit-stream.
The method of claim 6, wherein the synchronization procedure comprises:
- computing the deletion probabilities in the reconstructed appended bit-stream;
- and
- computing the insertion probabilities in the reconstructed appended bit-stream.
The method of claim 8, wherein the predetermined bit pattern is a non-zero bit pattern.
A memory controller comprising:
- a decoder to:
- receive a constrained codeword from a non-volatile memory (NVM) via a channel, the constrained codeword including an appended bit-stream;
- and
- decode the received constrained codeword by reconstructing the appended bit-stream and invoking a synchronization procedure that applies a maximum-likelihood (ML) estimator to estimate locations of any insertion, deletion, or error in the reconstructed appended bit-stream.
The memory controller of claim 14 further comprises:
- an encoder to:
- generate the appended bit stream by inserting bits that indicate which of a special pattern, from among special patterns, occurred in an input.
- append a one-bit to the appended bit-stream when the special pattern is mapped to another pattern;
- and
- append a zero-bit to the appended bit-stream when the special pattern remains is unchanged.
The memory controller of claim 15, wherein the encoder is operable to:
- append a predetermined bit pattern, at the end of the appended bit-stream, to terminate the Trellis.
The memory controller of claim 16, wherein the predetermined bit pattern is a non-zero bit pattern.
The memory controller of claim 20, wherein the decoder is further operable to:
- compute the deletion probabilities in the reconstructed appended bit-stream;
- and
- compute the insertion probabilities in the reconstructed appended bit-stream.
A system comprising:
- a solid state drive (SSD) comprising a memory controller coupled to a non-volatile memory (NVM) via a channel, the memory controller comprises:
- a decoder to:
- receive a constrained codeword from the NVM via the channel, the constrained codeword including an appended bit-stream;
- and
- decode the received constrained codeword by reconstructing the appended bit-stream and invoking a synchronization procedure that applies a maximum-likelihood (ML) estimator to estimate locations of any insertion, deletion, or error in the reconstructed appended bit-stream;
- and
- a display unit to display contents stored in the SSD.
The system of claim 24 further comprises:
- an encoder to:
- generate the appended bit stream by inserting bits that indicate which of a special pattern, from among special patterns, occurred in an input.
- append a one-bit to the appended bit-stream when the special pattern is mapped to another pattern;
- and
- append a zero-bit to the appended bit-stream when the special pattern remains is unchanged.
The system of claim 25, wherein the encoder is operable to:
- append a predetermined bit pattern, at the end of the appended bit-stream, to terminate the Trellis.
An article of manufacture having a machine storage medium containing machine executable instructions that when executed cause a processor to perform a method, the method comprising:
- receiving a constrained codeword from a non-volatile memory (NVM) via a channel, the constrained codeword including an appended bit-stream;
- and
- decoding the received constrained codeword by reconstructing the appended bit-stream and invoking a synchronization procedure that applies a maximum-likelihood (ML) estimator to estimate locations of any insertion, deletion, or error in the reconstructed appended bit-stream.
Dependencies are inferred from the claim text.