System and Method for Multi-Core Hardware Video Encoding And Decoding

A method for performing a coding operation on video data using a computing device that includes primary memory, a plurality of cores each having an associated memory, and a bus coupling the primary memory to one or more of the plurality of cores, the method comprising:

• storing the video data in the primary memory;
• loading, via the bus, at least a first portion of the video data from the primary memory into the associated memory of a first core of the plurality of cores;
• performing a coding operation, by the first core, on the first portion of the video data;
• loading a first reference portion from the first core into the associated memory of a second core of the plurality of cores, wherein the first reference portion is loaded directly without being stored in the primary memory;
• loading, via the bus, at least a second portion of the video data from the primary memory into the associated memory of the second core of the plurality of cores;
• and
• performing the coding operation, by the second core, on the second portion of the video data using the first reference portion as a reference.