Word line driver
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorSergiy ROMANOVSKYY
Life of this patent
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Abstract
A first circuit is coupled to a second circuit, which is coupled to a third circuit. A high voltage value of a first input signal and of a first output signal of the first circuit are equal, and are less than a high voltage value of a second output signal of the second circuit. A low voltage value of the first input signal is higher than a low voltage value of the first output signal. A high voltage value of the second output signal and of a third output signal of the third circuit are equal. The low voltage value of the first output signal, the second output signal, and the third output signal are equal.
Claims20
A word line driver circuit comprising:
- a first circuit configured to receive a first input signal and to generate a first output signal, the first input signal swinging between a high voltage value and a low voltage value of the first input signal, the first output signal swinging between a high voltage value and a low voltage value of the first output signal;
- a second circuit coupled to the first circuit and configured to receive the first output signal and to generate a second output signal, the second output signal swinging between a high voltage value and a low voltage value of the second output signal;
- and
- a third circuit coupled to the second circuit and configured to receive the second output signal and generate a third output signal, the third output signal swinging between a high voltage value and a low voltage value of the third output signal,
- wherein
- the high voltage value of the first input signal and of the first output signal are equal, and are less than the high voltage value of the second output signal;
- the low voltage value of the first input signal is higher than the low voltage value of the first output signal;
- the high voltage values of the second output signal and of the third output signal are equal;
- and
- the low voltage values of the first output signal, the second output signal, and the third output signal are equal.
A word line driver circuit comprising:
- a first inverter having a first input and a first output;
- a second inverter having a second input and a second output, the second input coupled to the first output;
- and
- a third inverter coupled having a third input and a third output, the third input coupled to the second output,
- wherein
- the third output is configured to provide a signal for a word line of a memory cell;
- the first inverter includes
- a P-side configured to receive a first P-side voltage value and having a first P-side driving capability;
- an N-side configured to receive a first N-side voltage value and having a first N-side driving capability weaker than the first P-side driving capability;
- the second inverter includes
- a P-side configured to receive a second voltage P-side voltage value and having a second P-side driving capability;
- an N-side configured to receive a second N-side voltage value and having a second N-side driving capability stronger than the second P-side driving capability;
- and
- the third inverter includes
- a P-side configured to receive a third voltage P-side voltage value;
- an N-side configured to receive a third N-side voltage value.
A word line driver circuit comprising:
- a first circuit;
- a second circuit coupled to the first circuit;
- and
- a third circuit coupled to the second circuit and having a PMOS transistor coupled in series with an NMOS transistor at an output node;
- wherein
- the first circuit is configured to convert a low logical value of a first input to a high logical value of a first output of the first circuit;
- the second circuit is configured to convert the high logical value of the first output to a low logical value of a second output of the second circuit;
- the low logical value of the second output equals a voltage value at a source of the NMOS transistor;
- and
- the output node is configured to provide a signal for a word line of a memory cell.
Dependencies are inferred from the claim text.