Semiconductor device having compensation capacitor to stabilize power supply voltage
AssigneeElpida Memory, Inc.
InventorsTomohiro KITANO, Hisayuki NAGAMINE
Life of this patent
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Abstract
Disclosed herein is a device that includes: first and second memory cell arrays arranged in a first direction; a plurality of first bump electrodes disposed between the first and second memory cell arrays and arranged in line in a second direction crossing the first direction; a plurality of second bump electrodes disposed between the first bump electrodes and the second memory cell arrays and arranged in line in the second direction; a first area being between the first and second bump electrodes; a plurality of third bump electrodes disposed in the first area; and a first capacitor formed in the third area.
Claims20
A device comprising:
- first and second memory cell arrays arranged in a first direction;
- a plurality of first bump electrodes disposed between the first and second memory cell arrays and arranged in line in a second direction crossing the first direction;
- a plurality of second bump electrodes disposed between the first bump electrodes and the second memory cell arrays and arranged in line in the second direction;
- a first area being between the first and second bump electrodes;
- a plurality of third bump electrodes disposed in the first area;
- and
- a first capacitor formed in the third area.
A device comprising:
- first and second memory cell arrays;
- a first data input/output circuit that performs a data transfer from and to the first memory cell array;
- a second data input/output circuit that performs a data transfer from and to the second memory cell array;
- a plurality of first bump electrodes arranged in a first area which is positioned between the first data input/output circuit and the second data input/output circuit;
- and
- a power compensation capacitor provided in the first area.
Dependencies are inferred from the claim text.