Semiconductor device and method of driving thereof

A semiconductor device, comprising:

• a first latch unit configured to latch write data based on a strobe signal;
• a second latch unit configured to receive the write data latched in the first latch unit based on a first clock signal;
• and
• a strobe generation unit configured to generate the strobe signal and supply the strobe signal to the first latch unit, the strobe generation unit including a first bit shift counter configured to receive the second clock signal and output a first bit shift signal having a logic level that is inverted every plural clock cycles of the second clock signal, a second bit shift counter configured to receive an inverting signal of the second clock signal and output a second bit shift signal having a logic level that is inverted every plural clock cycles of an inverted second clock signal, a first logic gate configured to output an AND arithmetic result of the first bit shift signal and the inverted second clock signal as a first strobe signal, and a second logic gate configured to output an AND arithmetic result of the second bit shift signal and the second clock signal as a second strobe signal.

A method for driving a semiconductor device including a first latch unit that latches write data based on a strobe signal, a second latch unit that receives the write data latched in the first latch part based on a first clock signal, and a strobe generation unit that generates the strobe signal and supplies the strobe signal to the first latch unit, the method comprising the steps of:

• generating a bit shift signal having a logic level that is inverted every plural clock cycles of a second clock signal;
• outputting the second clock signal as the strobe signal according to a logic level of the bit shift signal;
• and
• latching the write data in the first latch unit for at least a period of time that begins with a first strobe and ends with a second strobe,
• wherein the first and second strobes are consecutive strobes of the strobe signal and define a time interval therebetween that is larger than a period of the second clock signal but less than a period of the bit shift signal.