Silicon on insulator and thin film transistor bandgap engineered split gate memory

A method for operating a semiconductor structure, the semiconductor structure comprising a plurality of parallel semiconductor body regions over a substrate;

• a plurality of parallel word lines between a first select line and a second select line, the word lines including a selected word line and a plurality of unselected word lines, the word lines, the first select line and the second select line being over and substantially perpendicular to the semiconductor body regions;
• and a tunneling barrier, a charge storage layer and a dielectric layer between the word lines and the semiconductor body regions, wherein the semiconductor body regions include at least one first region adjacent to the first select line and the second select line and second regions between two neighboring word lines, wherein the first region has a dopant concentration higher than that of the second regions and wherein at least one of the second regions is junction-free, the method comprising:
• applying a first voltage to the first select line and the second select line;
• applying a second voltage to the word lines, the first voltage being higher than the second voltage;
• and
• applying a third voltage to the semiconductor body regions to reset the semiconductor structure, the third voltage being higher than the second voltage.

A method for forming a semiconductor structure, comprising:

• forming a plurality of first semiconductor body regions;
• forming a plurality of first word lines, each of the plurality of first word lines overlying a channel region in each of the first semiconductor body regions;
• forming a first tunneling barrier, a first charge storage layer, and a first dielectric layer between each of the first word lines and a corresponding channel region in each of the first semiconductor body regions, wherein the first semiconductor body regions between one of the first word lines and another one of the first word lines are junction-free;
• forming an inter-dielectric layer over the first word lines;
• forming a plurality of second semiconductor body regions overlying the inter-dielectric layer;
• forming a plurality of second word lines over the second semiconductor body regions;
• and
• forming a second tunneling barrier a second charge storage layer and a second dielectric layer between the second word lines and the second semiconductor body region.