US 2013/0258783 A1 · Method and Apparatus for Logic Read in Flash Memory

Abstract

The timing of logic read operations in a Flash memory device may be improved by a pad serial output circuit which receives a pre-decoded instruction signal and pre-fetched logic data prior to the last command clock, and which performs a fast resolution of the command in the pad serial output circuit on the last clock of the command input sequence. In one illustratively implementation, instruction pre-decode and data pre-fetch may be done on the seventh clock during command input. In another illustrative implementation, a first instruction pre-decode and data pre-fetch may be done on the fourth clock during command input, and a second instruction pre-decode may be done on the seventh clock during command input. Both serial protocol interface, including dual and quad I/O SPI, and quad peripheral interface are supported.

Claims12

Dependent claims

A Flash memory device which includes a capability of outputting logic data in response to a set of logic read commands, comprising:

an external signal input;
an addressable Flash memory cell array;
a data register coupled to the addressable Flash memory cell array for receiving and storing array data from the addressable Flash memory cell array;
a plurality of registers for storing logic data;
a command and control logic circuit comprising:
pre-fetch logic coupled to the external signal input for pre-fetching logic data from one of the logic data registers in accordance with a particular one of the plurality of logic read commands when a first partial sequence of most significant bits of a command received on the external signal input is predictive of the particular logic data read command;
and
output control logic coupled to the external signal input for generating a predicted logic read command signal when a second partial sequence of most significant bits of a command received on the external signal input is predictive of any one of the plurality of logic data read commands;
and
an output pad circuit coupled to the data register, the pre-fetch logic, the output control logic, and the external signal line for selecting and outputting the logic data from the pre-fetch logic when the predicted logic read command signal and a portion of the command other than the first and second partial sequences resolve receipt of any one of the plurality of logic data read commands.

7 more elements

Dependencies are inferred from the claim text.

Method and Apparatus for Logic Read in Flash Memory

Life of this patent

Method and Apparatus for Logic Read in Flash Memory

Life of this patent

Abstract

Claims12