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US 2013/0258781 A1Published application
Memory devices and biasing methods for memory devices
AssigneeMicron Technology, Inc.
InventorsAkira Goda, Yijie Zhao, Krishna Parat
Life of this patent
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Abstract
Devices, systems and methods of biasing in memory devices facilitate memory device programming and/or erase operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source where the data line and the source are biased to substantially the same potential during a programming and/or erase operation performed on one or more of the strings of memory cells.
Claims47
A method of operating a memory device, the method comprising:
- applying a first potential to a data line, where the data line is coupled to a first end of a first string of memory cells and to a first end of a second string of memory cells;
- applying a second potential to a select gate to deactivate the select gate, where the select gate is coupled between the first end of the second string of memory cells and the data line;
- applying a third potential to a source, where the source is coupled to a second end of the first string of memory cells and a second end of the second string of memory cells;
- and
- performing a programming operation on a selected memory cell of the first string of memory cells concurrently with biasing the data line to the first potential and while the select gate is deactivated;
- wherein the first potential is greater than the second potential.
3 more elements
A method of operating an array of memory cells, the method comprising:
- applying a potential to a data line, where the data line is coupled to a first end of a first string of memory cells and to a first end of a second string of memory cells;
- applying substantially the same potential to a source, where the source is coupled to a second end of the first string of memory cells and to a second end of the second string of memory cells;
- activating a first select gate coupled between the first end of the first string of memory cells and the data line;
- deactivating a second select gate coupled between the first end of the second string of memory cells and the data line where the potential applied to the data line is greater than a potential applied to the second select gate to deactivate the second select gate;
- and
- applying a programming potential to a selected memory cell of the first string of memory cells configured to increase a threshold voltage of the selected memory cell;
- wherein the programming potential is applied concurrently with applying substantially the same potential to the data line and source and with activating the first select gate and deactivating the second select gate.
4 more elements
A memory device, comprising:
- a data line;
- a source;
- a first string of memory cells coupled at a first end to the data line by a first select gate, and coupled at a second end to the source by a second select gate;
- a second string of memory cells coupled at a first end to the data line by a third select gate, and coupled at a second end to the source by a fourth select gate;
- and
- a controller, wherein the controller is configured to concurrently bias the data line and the source to substantially the same potential, bias a control gate of the third select gate to a potential less than the data line bias potential to deactivate the third select gate, and perform a program operation on a selected memory cell of the first string of memory cells.
3 more elements
A memory device, comprising:
- a plurality of strings of memory cells, where each string of memory cells is coupled at a first end to a data line by a drain select gate and where each string of memory cells is coupled at a second end to a source by a source select gate;
- and
- a controller, wherein the controller is configured to concurrently bias the data line and the source to a substantially same potential, perform a program operation on a selected memory cell of a selected string of memory cells while the data line and the source are biased to substantially the same potential, and to deactivate a particular drain select gate of an unselected string of memory cells while the data line and the source are biased to substantially the same potential;
- wherein the controller is further configured to bias a control gate of the particular drain select gate with a potential lower than the potential of the biased data line to deactivate the particular drain select gate.
1 more element
An electronic system, comprising:
- a communications interface;
- a memory access device coupled to the communications interface and configured to generate memory device commands;
- and
- a memory device coupled to the communications interface and configured to be responsive to the memory device commands, the memory device comprising:
- a data line;
- a source;
- a first string of memory cells coupled at a first end to the data line by a first select gate, and coupled at a second end to the source by a second select gate;
- a second string of memory cells coupled at a first end to the data line by a third select gate, and coupled at a second end to the source by a fourth select gate;
- and
- a controller, wherein the controller is configured to concurrently bias the data line and the source to substantially a same potential, bias a control gate of the third select gate to a potential less than the data line bias potential to deactivate the third select gate, and perform a program operation on a selected memory cell of the first string of memory cells.
7 more elements
A method of operating a memory device, the method comprising:
- biasing a data line to a first potential, where the data line is coupled to a first end of a first string of memory cells and to a first end of a second string of memory cells;
- biasing a source to a second potential, where the source is coupled to a second end of the first string and to a second end of the second string of memory cells;
- deactivating a select gate coupled between the first end of the second string of memory cells and the data line by biasing a control gate of the select gate to a third potential where the first potential is greater than the third potential;
- and
- performing a programming operation on a selected memory cell of the first string of memory cells concurrently with biasing the data line to the first potential and biasing the source to the second potential and while the select gate is deactivated;
- wherein the first potential is greater than the second potential.
3 more elements
A memory device, comprising:
- a data line;
- a source;
- a first string of memory cells coupled at a first end to the data line by a first select gate, and coupled at a second end to the source by a second select gate;
- a second string of memory cells coupled at a first end to the data line by a third select gate, and coupled at a second end to the source by a fourth select gate;
- and
- a controller, wherein the controller is configured to concurrently bias the data line to a first potential and to bias the source to a second potential, bias a control gate of the third select gate to a third potential to deactivate the third select gate, and perform a program operation on a selected memory cell of the first string of memory cells;
- wherein the first potential comprises a positive potential;
- and
- wherein the first potential is greater than the third potential.
6 more elements
A method of operating a memory device, the method comprising:
- biasing a data line to a first potential, where the data line is coupled to a first end of a first string of memory cells and to a first end of a second string of memory cells;
- biasing a source to a second potential substantially the same as the first potential, where the source is coupled to a second end of the first string and to a second end of the second string of memory cells;
- deactivating a select gate coupled between the first end of the second string of memory cells and the data line by biasing a control gate of the select gate to a third potential where the first potential is greater than the third potential;
- and
- performing a programming operation on a selected memory cell of the first string of memory cells concurrently with biasing the data line to the first potential and the source to the second potential and while the select gate is deactivated.
2 more elements
A method of operating a memory device, the method comprising:
- biasing a data line to a first potential, where the data line is coupled to a first end of a first string of memory cells and to a first end of a second string of memory cells;
- biasing a source to a second potential, where the source is coupled to a second end of the first string and to a second end of the second string of memory cells;
- deactivating a first select gate coupled between the first end of the second string of memory cells and the data line by biasing a control gate of the select gate to a third potential where the first potential is greater than the third potential;
- biasing a second and a third select gate to a third potential substantially equal to the second potential, where the second select gate is coupled between the second end of the first string of memory cells and the source, and where the third select gate is coupled between the second end of the second string of memory cells and the source;
- and
- performing a programming operation on a selected memory cell of the first string of memory cells concurrently with biasing the data line to the first potential, biasing the source to the second potential, and biasing the second select gate and third select gate to the third potential while the first select gate is deactivated.
3 more elements
Dependencies are inferred from the claim text.