Nand memory array with mismatched cell and bitline pitch

A three-dimensional (3-D) memory array comprising:

• a plurality of wordlines;
• a plurality of active area pillars;
• memory cells disposed at intersections of the plurality of active area pillars and the plurality of wordlines, the memory cells having a first pitch in a direction of the plurality of wordlines;
• and
• a plurality of bitlines arranged orthogonal to the plurality of wordlines, the plurality of bitlines having a second pitch that is less than the first pitch.

A non-volatile storage chip comprising:

• a package;
• input/output connections;
• and
• the 3-D memory array disposed within the package and electrically coupled with the input/output connections.

A method of operating a memory array comprising:

• simultaneously driving first and second sub-blocks of a block of memory cells of a memory array;
• accessing memory cells on a first plurality of NAND strings that correspond to first subset of bitlines of the first sub-block;
• and
• accessing memory cells on a second plurality of NAND strings that correspond to a second subset of bitlines of the second sub-block, wherein the first and second sub-blocks blocks are adjacent and the first plurality of NAND strings are offset with respect to the second plurality of NAND strings.

A system comprising:

• a communication interface having one or more antennas configured to communicatively couple the system to a wireless network;
• a NAND memory array having a cell pitch in a direction of a wordline of the NAND memory array, and a bitline pitch in the direction of the wordline, wherein the cell pitch is different from the bitline pitch;
• and
• system control logic coupled with the communication interface and the NAND memory array, wherein the system control logic is configured to provide one or more interfaces to move data into or out of the communication interface and the NAND memory array.