Non-Volatile Memory and Method Having a Memory Array with a High-Speed, Short Bit-Line Portion

A method of operating a non-volatile memory device having an array of memory cells, comprising:

• accessing said array of memory cells with rows of word lines and columns of bit lines;
• partitioning said array of memory cells along a column direction into a first array portion and a second array portion, said first array portion being adjacent a set of read/write circuit;
• configuring memory cells of said first array portion to operate as single-level cells each storing one bit of data;
• configuring memory cells of said second portion to operate as multi-level cells each storing more than one bit of data;
• partitioning said columns of bit lines into a first segment of bit lines corresponding to said first array portion and a second segment of bit lines corresponding to said second array portion
• said first segment of bit lines having first ends adjacent the set of read/write circuits and second ends adjacent the second segment of bit lines;
• providing a switchable couplings between the second ends of the first segment of bit lines and the second segment of bit lines;
• coupling first ends of said first segment of bit lines to the set of read/write circuits and switching off the switchable coupling between the second ends of the first segment of bit lines and the second segment of bit lines when reading and writing in parallel a group of memory cells of the first array portion;
• and
• coupling first ends of said first segment of bit lines to the set of read/write circuits and switching on the switchable coupling between the second ends of the first segment of bit lines and the second segment of bit lines when reading and writing in parallel a group of memory cells of the second array portion.