Vertical transistor, memory cell, device, system and method of forming same
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is fowled in the substrate and a body region and a second source/drain region are formed within the pillar. A first gate is coupled to a first side of the pillar for coupling the first and second source/drain regions together when activated. The vertical memory cell also includes a storage capacitor formed on an extended end of the semiconducting pillar and electrically coupled to the second source/drain region.
Claims21
A semiconductor device, comprising:
- a pillar of semiconductor material extending from a substrate and including a body region over the substrate and a second source/drain region over the body region;
- a bit line formed in the substrate and at least partially offset from the pillar in a direction lateral to the bit line;
- and
- a first source/drain region coupled to the bit line and at least partially under the body region, wherein the first source/drain region, the body region and the second source/drain region comprise elements of an access transistor.
A method of forming a semiconductor device, comprising:
- forming a pillar of semiconductor material over a substrate, the pillar comprising a body region of an access transistor over the substrate and a second source/drain region of the access transistor over the body region;
- forming a bit line in the substrate, wherein the bit line is at least partially offset from the pillar in a direction lateral to the bit line;
- and
- forming a first source/drain region of the access transistor, wherein the first source/drain region is in conductive contact with the bit line and is at least partially under the body region of the pillar.
A method of using a semiconductor device, comprising:
- controlling conductive characteristics of an access transistor with a first signal applied to a first gate of the access transistor disposed on a first side of a pillar configured as a vertical transistor with a first source/drain region coupled to a bit line in a substrate, a body region over the first source/drain region, and a second source/drain region above the body region;
- and
- modifying the conductive characteristics of the access transistor with a second signal applied to a second gate of the access transistor disposed on a second side of the pillar.
Dependencies are inferred from the claim text.