Conduction cooling of multi-channel flip chip based panel array circuits

An assembly of semiconductor integrated circuit (IC) chips, the assembly comprising:

• a substrate having a top surface;
• a first semiconductor IC chip having corresponding first and second opposing surfaces, wherein at least a portion of the first surface of the first semiconductor IC chip is coupled to the top surface of the substrate and wherein the first semiconductor chip has a first height;
• a second semiconductor IC chip having corresponding first and second opposing surfaces, where at least a portion of the first surface of the second semiconductor IC chip is coupled to the top surface of the substrate and wherein the second semiconductor chip has a second height different than the first height;
• a first portion of a first thermal spreader material coupled to the second surface of the first semiconductor IC chip, the first portion having a first thickness, wherein the combination of the first height and the first thickness results in a first total height;
• and
• a second portion of a second thermal spreader material coupled to the second surface of the second semiconductor IC chip, the second portion having a second thickness, wherein the combination of the second height and the second thickness results in a second total height, wherein the second total height is substantially the same as the first total height, such that the first total height and second total height are substantially coplanar.

A system for cooling a plurality of semiconductor integrated circuit (IC) sub-assemblies, the system comprising at least one assembly comprising:

• a thermal dissipation member, the thermal dissipation member having an upper surface and a substantially planar lower surface;
• and
• a plurality of sub-assemblies coupled to the lower surface of the thermal dissipation member, at least two of the plurality of sub-assemblies having an upper surface that is coplanar with each other, each respective sub-assembly of the at least two sub-assemblies comprising:
• a sub-assembly substrate having a top surface;
• a first semiconductor IC chip having corresponding first and second opposing surfaces, wherein at least a portion of the first surface of the first semiconductor IC chip is coupled to the top surface of the sub-assembly substrate and wherein the first semiconductor chip has a first height;
• a second semiconductor IC chip having corresponding first and second opposing surfaces, where at least a portion of the first surface of the second semiconductor IC chip is coupled to the top surface of the sub-assembly substrate and wherein the second semiconductor chip has a second height, wherein the second height is different than the first height;
• a first portion of a first thermal spreader material coupled to the second surface of the first semiconductor IC chip, the first portion having a first thickness, wherein the combination of the first height and the first thickness results in a first total height;
• and
• a second portion of a second thermal spreader material coupled to the second surface of the second semiconductor IC chip, the second portion having a second thickness, wherein the combination of the second height and the second thickness results in a second total height, wherein the second total height is substantially the same as the first total height, such that the first total height and second total height are substantially coplanar.