US 2013/0257635 A1 · DIGITAL CORRECTION CIRCUIT FOR A PIPELINED ANALOG-TO-DIGITAL CONVERTER

Abstract

A digital correction circuit for a pipelined analog-to-digital converter (ADC) is disclosed. Compared to the conventional digital correction circuit which uses adders to perform operations in ADC digital correction part and hence needs a rather long operation time, the digital correction circuit of this invention can reduce the time needed in operations in the finial digital correction circuits and thus can optimize operation time, by allocating the operations to a plurality of pipeline stages of second sub-circuits configured to synchronize digital codes, each of which can perform part of the operations only with NAND gates, NOR gates, phase inverters and D-type flip-flops, without needing to use adders.

A digital correction circuit for a pipelined analog-to-digital converter (ADC), the pipelined ADC including N stages of first sub-circuits, each of which outputting a 2-bit code, the 2-bit code output by the n-th-stage of first sub-circuit being expressed as D2(N+1−n) and D2(N+1−n), where N is an integer greater than 3 and n is an integer satisfying 1≦n≦N, the digital correction circuit comprising N stages of second sub-circuits, among which:

the first-stage of second sub-circuit is configured to receive the 2-bit code D2N and D2N-1 output by the first-stage of first sub-circuit;
the i-th-stage of second sub-circuit is configured to receive both the 2-bit code D2(N+1-i) and D2(N+1-i)-1 output by the i-th-stage of first sub-circuit and an output from the (i−1)-th-stage of second sub-circuit, where i is an integer satisfying 2≦i≦N−1;
and the N-th-stage of second sub-circuit is configured to receive D2;
wherein the digital correction circuit outputs N+1 quantized bits, including a first quantized bit Q1 that equals to D1 and second to (N+1)-th quantized bits Q2 to QN+1 that are output by the N-th-stage of second sub-circuit, among which:
the quantized bit QN+1 is expressed as QN+1=AN+1,2+BN+1,2D2, where AN+1,2 and BN+1,2 are coefficients of an (N−1)-th-stage of intermediate value that is output by the (N−1)-th-stage of second sub-circuit and corresponds to the quantized bit QN+1, coefficients of the respective stages of intermediate values that are output by the respective stages of second sub-circuits and correspond to the quantized bit QN+1 satisfying the following recurrence relations:
A
N
+
1
,
m
=
{
A
N
+
1
,
m
+
1
+
B
N
+
1
,
m
+
1

D
2

m
(
m
=
2
,
3
,
…

,
N
-
2
)
D
2

N
+
D
2

N
-
1

D
2

N
-
2
(
m
=
N
-
1
)


B
N
+
1
,
m
=
{
B
N
+
1
,
m
+
1

D
2

m
_

D
2

m
-
1
(
m
=
3
,
4
,
…

,
N
-
2
)
B
N
+
1
,
3

D
3
(
m
=
2
)
D
2

N
-
1

D
2

N
-
2
_

D
2

N
-
3
(
m
=
N
-
1
)
the quantized bit Qk is expressed as Qk=Ak,2 D2+Bk,2+Ek,2D2 where k is an integer satisfying 3≦k≦N, Ak,2, Bk,2, and Ek,2 are coefficients of an (N−1)-th-stage of intermediate value that is output by the (N−1)-th-stage of second sub-circuit and corresponds to the quantized bit Qk, coefficients of the respective stages of intermediate values that are output by the respective stages of second sub-circuits and correspond to the quantized bit Qk satisfying the following recurrence relations:

A
k
,
m
=
{
D
2

m
+
1

D
2

m
_
(
m
=
k
-
1
)
A
k
,
m
+
1

D
2

m
_
(
m
=
2
,
3
,
…


k
-
2
)


B
k
,
m
=
{
D
2

m
+
1

D
2

m
_


D
2

m
-
1
_
+
D
2

m
+
1
_

D
2

m
(
m
=
k
-
1
)
A
k
,
m
+
1

D
2

m
_


D
2

m
-
1
_
+
B
k
,
m
+
1
+
E
k
,
m
+
1

D
2

m
(
m
=
2
,
3
,
…


k
-
2
)



E
k
,
m
=
{
D
2

m
+
1
_


D
2

m
_

D
2

m
-
1
(
m
=
k
-
1
)
E
k
,
m
+
1

D
2

m
_

D
2

m
-
1
(
m
=
3
,
4
,
…


k
-
2
)
E
k
,
3

D
3
(
m
=
2
)
;
and the quantized bit Q2 is expressed as Q2=D3 D2+ D3D2.

398 more elements

Digital correction circuit for a pipelined analog-to-digital converter

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Digital correction circuit for a pipelined analog-to-digital converter

Life of this patent

Abstract

Claims3