US 2013/0257546 A1Published application

Phase locked loop with adaptive loop filter

AssigneeFreescale Semiconductor, Inc.

InventorDashun Xue

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Abstract

A PLL including an adaptive loop filter. The PLL includes a feedback circuit which provides a feedback signal based on an output signal and a phase detector generating an adjust signal based on a frequency of the feedback signal compared with a reference frequency. A charge pump receives the adjust signal and provides a control voltage. The adaptive loop filter includes a capacitor and an adaptive resistance with a current control input. A VCO has an output providing the output signal based on a voltage level of the control voltage. A bias generator converts the control voltage to a loop bias current, and has a bias output based on the loop bias current coupled to the current control input of the adaptive resistance. The bias output of the bias generator may also be used to control the charge current and the VCO using currents proportional to the loop bias current.

Claims20

Dependent claims

A phase locked loop, comprising:

a feedback circuit which provides a feedback signal based on an output signal, and a phase detector which generates at least one adjust signal based on a frequency of said feedback signal compared with a reference frequency;
a charge pump receiving said at least one adjust signal and having an output coupled to a control node providing a control voltage;
a capacitor and an adaptive resistance coupled in series between said control node and a reference node, wherein said adaptive resistance includes at least one current control input;
a voltage controlled oscillator having an output providing said output signal based on a voltage level of said control voltage;
a bias generator which converts said control voltage to a loop bias current, and which has at least one bias output which is based on said loop bias current and which is coupled to said at least one current control input of said adaptive resistance;
and
wherein said bias generator provides a bias voltage, and wherein said adaptive resistance comprises:
a first transistor having a source coupled to a source voltage, having a gate receiving said bias voltage, and having a drain;
a second transistor having a drain and gate coupled to said drain of said first transistor and having a source coupled to said reference node;
and
a third transistor having a drain coupled to said capacitor, having a gate coupled to said gate of said second transistor, and having a source coupled to said reference node.

8 more elements

A phase locked loop, comprising:

a feedback circuit which provides a feedback signal based on an output signal, and a phase detector which generates at least one adjust signal based on a frequency of said feedback signal compared with a reference frequency;
a charge pump receiving said at least one adjust signal and having an output coupled to a control node providing a control voltage;
a capacitor and an adaptive resistance coupled in series between said control node and a reference node, wherein said adaptive resistance includes at least one current control input;
a voltage controlled oscillator having an output providing said output signal based on a voltage level of said control voltage;
a bias generator which converts said control voltage to a loop bias current, and which has at least one bias output which is based on said loop bias current and which is coupled to said at least one current control input of said adaptive resistance, wherein said bias generator comprises:
a first transistor having a source coupled to a source voltage and having a drain and gate coupled together at a first bias node;
a second transistor having a source coupled to said source voltage, having a gate coupled to said first bias node, and having a drain;
a third transistor having a drain coupled to said drain of said first transistor, having a gate coupled to said control node, and having a source coupled to said reference node;
and
a fourth transistor having a drain and gate coupled together to said drain of said second transistor at a second bias node, and having a source coupled to said reference node;
and
wherein said adaptive resistance comprises:
a fifth transistor having a source coupled to a source voltage, having a gate coupled to said first bias node, and having a drain;
a sixth transistor having a drain and gate coupled to said drain of said fifth transistor and having a source coupled to said reference node;
and
a seventh transistor having a drain coupled to said capacitor, having a gate coupled to said gate of said sixth transistor, and having a source coupled to said reference node.

13 more elements

Dependencies are inferred from the claim text.