High speed duty cycle correction and double to single ended conversion circuit for pll
AssigneeChina Electronic Technology Corporation
InventorsYouhua Wang, Junan Zhang, Dongbing Fu, Gangyi Hu, Jun Liu, Ruzhang Li, Guangbing Chen
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Abstract
The present invention pertains to a high speed duty cycle correction and double to single ended conversion circuit for PLL, comprising a reshaper stage, a single-edge detection circuit and a duty cycle restorer. The present invention introduces a way to convert double-ended output of PLL VCO into single-ended signal and adjust duty cycle of PLL VCO's output waveform by 50%, so that the circuit can output single ended clock signal with 50% duty cycle.
Claims9
A high speed duty cycle correction and a double to single ended conversion circuit for PLL, wherein
- A clock input reshaper stage, comprising two clock input reshaping circuits I and II, respectively, receiving signals 180° out of phase, output a powerful driving clock signal;
- A single-edge detection circuit, comprising two single-edge detection circuit I and II, respectively, receiving signals from clock input reshaping circuit I and II, detects rising and falling edge of clock signal and then outputs pulse signals;
- A duty cycle restorer receives pulse signals 180° out of phase from two single-edge detection circuits I and II, and then outputs 50% duty cycle clock signals with the same frequency as pulse signals.
Dependencies are inferred from the claim text.