Receiver circuit for receiving an input signal
AssigneeAms AG
InventorBernhard GREIMEL-RECHLING
Life of this patent
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AssigneeAms AG
InventorBernhard GREIMEL-RECHLING
Estimating the term…
A receiver circuit for receiving an input signal (IDD, UDD) comprises a detector circuit (111, 111a, 111b, 111c, 111d, 111e, 111f), which is in the form of a sample-and-hold circuit for determining a reference level of the input signal or in the form of a filter circuit for generating a mean value of levels of the input signal (IDD, UDD). The detector circuit generates, on the output side, a referential signal (RS), which is supplied to comparator circuits (113a, 113b, 113c, 113d, 115a, 115b, 115c, 115d). The comparator circuits (113a, 113b, 113c, 113d, 115a, 115b, 115c, 115d) compare an offset level of the input signal (IDD, UDD) with the referential signal (RS) and generate data signals (DATA, DH, DL). The offset input signals (IDD, UDD) are evaluated relatively in respect of the reference level or the mean value of the levels of the input signal.
A receiver circuit for receiving an input signal, comprising:
A method for evaluating an input signal for a receiver circuit for generating a data signal, comprising:
Dependencies are inferred from the claim text.