Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts

A method for fabricating an integrated circuit having a substrate contact, the method comprising:

• depositing a first stress-inducing layer overlying a first device region and a second device region of an SOI substrate, wherein the first device region has a first transistor and a second transistor that are formed therein, and wherein the second device region has a first trench that extends through a buried insulating layer to a silicon substrate of the SOI substrate and a metal silicide region that is formed in the silicon substrate exposed by the first trench;
• etching a first portion of the first stress-inducing layer that overlies the second transistor while covering a second remaining portion of the first stress-inducing layer that overlies the first transistor and the second device region;
• depositing a second stress-inducing layer overlying the first and second device regions, wherein the second stress-inducing layer has a different type of intrinsic stress than the first stress-inducing layer;
• etching a third portion of the second stress-inducing layer that overlies the first transistor while covering a fourth remaining portion of the second stress-inducing layer that overlies the second transistor and the second device region;
• depositing an ILD layer of dielectric material overlying the first and second device regions;
• etching a second trench in the second device region extending through the ILD layer and the first and second stress-inducing layers that are disposed in the first trench to expose the metal silicide region;
• and
• filling the second trench with a conductive material.

An integrated circuit including a substrate contact, the integrated circuit comprising:

• a SOI substrate having a semiconductor layer, a silicon substrate, and a buried insulating layer that is disposed between the semiconductor layer and the silicon substrate;
• a metal silicide region disposed in the silicon substrate, wherein the SOI substrate has a filled trench formed therein extending through the buried insulating layer to the metal silicide region;
• a first stress-inducing layer disposed in the filled trench overlying the metal silicide region;
• a second stress-inducing layer disposed in the filled trench overlying the first stress-inducing layer, wherein the second stress-inducing layer has a different type of intrinsic stress than the first stress-inducing layer;
• an ILD layer of dielectric material overlying the second stress-inducing layer;
• and
• the substrate contact comprising a conductive material extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region.