Grid fan-out wafer level package and methods of manufacturing a grid fan-out wafer level package
AssigneeIntel Mobile Communications GmbH
InventorThorsten Meyer
Life of this patent
Estimating the term…
Abstract
In various aspects of the disclosure, a chip packaging arrangement may be provided. The chip packaging arrangement may include a dielectric layer with at least one semiconductor device adjoining the dielectric layer, at least one bonding area on the semiconductor device, the bonding area being exposed through the dielectric layer, a first material comprising a first coefficient of thermal expansion substantially surrounding the semiconductor device and adjoining the dielectric layer, a second material comprising a second coefficient of thermal expansion substantially surrounding the semiconductor device and the first material; and at least one conductive trace electrically connected to the semiconductor device.
Claims25
A chip packaging arrangement, comprising:
- a dielectric layer;
- at least one semiconductor device adjoining the dielectric layer;
- at least one bonding area on the at least one semiconductor device, the bonding area being exposed through the dielectric layer;
- a first material comprising a first coefficient of thermal expansion substantially surrounding the at least one semiconductor device and adjoining the dielectric layer and;
- a second material comprising a second coefficient of thermal expansion substantially surrounding the at least one semiconductor device and the first material.
A method of manufacturing a chip packaging arrangement, the method comprising:
- providing at least one semiconductor device;
- forming at least one contact on the at least one semiconductor device;
- surrounding the at least one semiconductor device with a first material comprising a first coefficient of thermal expansion;
- forming a first layer by surrounding the first material and the at least one semiconductor device with a second material comprising a second coefficient of thermal expansion;
- forming a partial layer of dielectric adjoining the first material and the at least one semiconductor device.
A chip packaging arrangement, comprising:
- at least one semiconductor device comprising an electrical contact;
- a first material comprising a first coefficient of thermal expansion adjoining a dielectric material and at least partially surrounding the semiconductor device;
- a second material comprising a second coefficient of thermal expansion at least partially surrounding the semiconductor device and the first material.
The chip packaging arrangement of claim 23, wherein the redistribution trace is further connected to a printed circuit board via electrical connection means.
A chip packaging arrangement, comprising:
- a first layer comprising a semiconductor device having an electrical contact, the semiconductor device comprising a first coefficient of thermal expansion;
- a first material comprising a second coefficient of thermal expansion adjoining a dielectric material and at least partially surrounding the semiconductor device in the first layer;
- a second material comprising a third coefficient of thermal expansion at least partially surrounding the semiconductor device and the first material in the first layer;
- a second layer comprising the second material adjoining the first layer.
A device, comprising:
- a first layer comprising a semiconductor device comprising an electrical contact, the semiconductor device comprising a first coefficient of thermal expansion;
- a first material comprising a second coefficient of thermal expansion adjoining a dielectric material and at least partially surrounding the semiconductor device in the first layer;
- a second material comprising a third coefficient of thermal expansion at least partially surrounding the semiconductor device and the first material in the first layer;
- a second layer comprising the second material adjoining the first layer.
Dependencies are inferred from the claim text.