Semiconductor chip device with fragmented solder structure pads
OwnerRoden R. Topacio, Neil McLellaninventors
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Abstract
Methods and apparatus to inhibit cracks and delaminations in a semiconductor chip solder bump and to reduce pad parasitic capacitance are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first insulating layer over plural conductor pads of a semiconductor chip and forming an opening over each of the conductor pads. An individual solder structure is coupled to the insulating layer. The solder structure has a projection in each of the openings and in electrical contact with one of the plural conductor pads.
Claims20
A method of manufacturing, comprising:
- forming a first insulating layer over plural conductor pads of a semiconductor chip;
- and
- forming an opening over each of the conductor pads;
- and
- coupling an individual solder structure to the insulating layer, the solder structure having a projection in each of the openings and in electrical contact with one of the plural conductor pads.
A method of coupling a semiconductor chip to a circuit board, comprising:
- placing plural projections of a first individual solder structure in corresponding plural openings in an insulating layer of the semiconductor chip, each of the openings being over one of plural conductor pads;
- coupling the first solder structure to the circuit board.
An apparatus, comprising:
- a semiconductor chip having plural conductor pads;
- an insulating layer on the plural conductor pads, the insulating layer having an opening over each of the plural conductor pads;
- and
- an individual solder structure on the insulating layer, the solder structure having a projection in each of the openings and in electrical contact with one of the plural conductor pads.
Dependencies are inferred from the claim text.