ROM Arrays Having Memory Cell Transistors Programmed Using Metal Gates
AssigneeBroadcom Corporation
InventorWei Xia
Life of this patent
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Abstract
According to one exemplary implementation, an integrated circuit (IC) includes a first memory cell transistor of a read only memory (ROM) array, the first memory cell transistor including a first metal gate of a first work function and having a first threshold voltage. The IC also includes a second memory cell transistor of the ROM array, the second memory cell transistor including a second metal gate of a second work function and having a second threshold voltage. The first memory cell transistor and the second memory cell transistor can be of a first conductivity type. Furthermore, the first memory cell transistor can include a first high-k gate dielectric and the second memory cell transistor can include a second high-k gate dielectric.
Claims20
An integrated circuit (IC) comprising:
- a first memory cell transistor of a read only memory (ROM) array, said first memory cell transistor comprising a first metal gate of a first work function and having a first threshold voltage;
- a second memory cell transistor of said ROM array, said second memory cell transistor comprising a second metal gate of a second work function and having a second threshold voltage.
A method for fabricating an integrated circuit (IC), said method comprising:
- forming, from a first metal gate layer, a first metal gate of a first memory cell transistor of a read only memory (ROM) array, said first metal gate of a first work function and having a first threshold voltage;
- forming, from a second metal gate layer, a second metal gate of a second memory cell transistor of said ROM array, said second metal gate of a second work function and having a second threshold voltage.
A method for fabricating an integrated circuit (IC), said method comprising:
- forming, from a first metal gate layer, a first metal gate of a first N type memory cell transistor of a read only memory (ROM) array, said first metal gate of a first work function and having a first threshold voltage;
- forming, from a second metal gate layer, a second metal gate of a second N type memory cell transistor of said ROM array, said second metal gate of a second work function and having a second threshold voltage.
Dependencies are inferred from the claim text.