# US 2013/0254591 A1 · Method and device for enhancing the reliability of a multiprocessor system by hybrid checkpointing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0254591 A1 - Document ID: US20130254591A1 - Status: Published application - Kind: A1 - Application number: 13/991,128 - Filed: 2011-11-24 - Published: 2013-09-26 - Earliest claimed: 2010-12-01 - Assignees: Commissariat A L'energie Atomique Et Aux Energies Alternatives - Inventors: Cartron Mickaël; Yoann Congal - Web page: https://patentgrep.com/patent/US20130254591A1 ## CPC - G06F 11/1008: {in individual solid state devices (G06F11/1004 takes precedence)} - G06F 11/1402: {Saving, restoring, recovering or retrying} - G06F 11/141: {for bus or memory accesses} - G06F 11/1438: {Restarting or rejuvenating} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The present invention relates to a method and a device for enhancing the reliability of a system comprising a plurality of processors and a memory. The method comprises a step of grouping processes into a plurality of groups and a step of saving, individually for each group of processes, data stored in the memory which can be used by at least one of the processes belonging to said group, so as to restore an error-free global state of the system following an error occurring in a processor executing one of the processes belonging to said group without having to restore the entire memory. ## Claims ### Claim 1 A method of enhancing the reliability of a system comprising a plurality of processors and a memory, the method comprising: grouping processes into a plurality of groups, each group being a data dependency sphere grouping processes that access areas of the memory, wherein: a union of the access areas is logically connected, and each of the access areas has a non-empty intersection with the union of all other access areas among said access areas; saving, individually for each group of processes, data stored in the memory, the data being used by at least one of the processes belonging to said group, to restore an error-free global state of the system following an error occurring in one of the processors executing one of the processes belonging to said group, without restoring the entire memory, and, confining accesses to the memory by data dependency sphere, by: managing access rights to the memory areas for each process to prevent propagation of a logic error occurring in the processor executing said process; and managing indicators of memory areas belonging to each data dependency sphere. ### Claim 2 A device for enhancing the reliability of a system comprising a plurality of processors and a memory, the device comprising: means for grouping processes into a plurality of groups, said means grouping the processes by data dependency spheres, each data dependency sphere grouping processes that access areas of the memory, wherein: a union of the access areas is logically connected, and each of the access areas has a non-empty intersection with the union of all other areas among said access areas; means for saving individually for each group of processes the data stored in the memory, the data being used by at least one of the processes belonging to said group, to restore an error-free global state of the system following an error occurring in one of the processors executing one of the processes belonging to said group, without restoring the entire memory, and, means for confining accesses to the memory by data dependency sphere, the means for confining comprising: means for managing access rights to the memory areas for each process to prevent propagation of a logic error occurring in the processor executing said process; and means for managing indicators of memory areas belonging to each data dependency sphere. ### Claim 3 (depends on 2) The device as claimed in claim 2, wherein, for each data dependency sphere, the saved data comprise: the data stored in a connected union of the memory areas that can be accessed by one of the processes belonging to said sphere, the data stored in registers of the processors executing one of the processes belonging to said sphere, data stored in pipeline stages of the processors executing one of the processes belonging to said sphere, data stored in memory management units or in memory protection units (MPU) included in the processors executing one of the processes belonging to said sphere, or data stored in cache memories of the processors executing one of the processes belonging to said sphere. ### Claim 4 (depends on 2) The device as claimed in claim 2, wherein the means for grouping the processes into data dependency spheres are implemented in the form of services supplied by an operating system of the system, the services supplying the data dependency spheres corresponding to all currently executed processes. ### Claim 5 (depends on 4) The device as claimed in claim 4, wherein the means for saving include means for coordinating saving of the data dependency spheres corresponding to all currently executed processes, the means for coordinating comprising: means for initiating a data save for a data dependency sphere corresponding to currently executed processes; and means for initiating, following the logic error that has occurred in one of the processors executing one of the processes belonging to said sphere, restoration of the data saved for said data dependency sphere exclusively. ### Claim 6 (depends on 2) The device as claimed in claim 2, characterized in that the means for confining include a memory management unit or a memory protection unit associated with each of the processors of the system, said unit denying to the processor with which it is associated access to the memory outside the area allocated to the process being executed by said processor. ### Claim 7 (depends on 6) The device as claimed in claim 6, wherein the memory management unit or the memory protection unit includes means for managing memory access rights, the current data dependency spheres being dependent on the memory access rights.