# US 2013/0254584 A1 · Sequencer system and control method therefor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0254584 A1 - Document ID: US20130254584A1 - Status: Published application - Kind: A1 - Application number: 13/990,501 - Filed: 2010-12-16 - Published: 2013-09-26 - Earliest claimed: 2010-12-16 - Assignees: Mitsubishi Electric Corporation - Inventors: Morimichi Tamaoki - Web page: https://patentgrep.com/patent/US20130254584A1 ## CPC - G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators} - G05B 19/05: Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts - G05B 2219/13063: Synchronization between modules - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G) ## Abstract A sequencer system includes a plurality of units, a backplane on which the units are mounted, bus communication lines for data transmission and reception among the units, a clock generation unit that generates a fixed-cycle clock signal having an arbitrary cycle, and an electric signal line provided separately from the bus communication lines, to transfer the fixed-cycle clock signal from the clock generation unit to the units via the backplane. Each of the units includes a processor that controls the unit, and an interrupt-signal control unit that generates an interrupt signal corresponding to the fixed-cycle clock signal. The processor uses the interrupt signal to synchronize control timings of the units. ## Claims ### Claim 1 A sequencer system comprising: a plurality of units; a backplane on which the units are mounted; a bus communication line for data transmission and reception among the units; a clock generation unit that generates a fixed-cycle clock signal having an arbitrary cycle; and an electric signal line that is provided separately from the bus communication line, and transfers the fixed-cycle clock signal from the clock generation unit to the units via the backplane, wherein each of the units includes a processor that controls the unit, and an interrupt-signal control unit that generates an interrupt signal corresponding to the fixed-cycle clock signal, and the processor uses the interrupt signal to synchronize control timings of the units. ### Claim 2 (depends on 1) The sequencer system according to claim 1, wherein the unit further includes a counter control unit that controls a synchronous counter, the counter control unit executes zero clear of the synchronous counter depending on the fixed-cycle clock signal, and causes the synchronous counter to count up in a same operating frequency in the respective units, and the interrupt-signal control unit generates the interrupt signal depending on a value of the synchronous counter. ### Claim 3 (depends on 1) The sequencer system according to claim 1, wherein the clock generation unit is provided in any of a master unit that manages an entire system among the plurality of units, the units other than the master unit, and the backplane. ### Claim 4 (depends on 1) The sequencer system according to claim 1, further comprising a communication-relay processing unit that controls data transmission and reception among the units by relaying, wherein the communication-relay processing unit is provided in either the units or the backplane. ### Claim 5 (depends on 1) The sequencer system according to claim 1, wherein the electric signal line transfers the fixed-cycle clock signal to all the units constituting the sequencer system, and the units can select whether to execute synchronous control by the fixed-cycle clock signal. ### Claim 6 (depends on 1) The sequencer system according to claim 1, further comprising a selector unit that can selectively switch connection and disconnection of the electric signal line, wherein the clock generation unit is provided in each group acquired by grouping the units by disconnection of the electric signal line in the selector unit. ### Claim 7 (depends on 6) The sequencer system according to claim 6, wherein the clock generation units provided in respective groups acquired by grouping the units generate the fixed-cycle clock signals having a frequency different from each other. ### Claim 8 (depends on 1) The sequencer system according to claim 1, further comprising the electric signal lines, wherein the units can be grouped by selection of the electric signal lines, and the clock generation unit is provided in respective groups of the units grouped by the selection of the electric signal lines. ### Claim 9 (depends on 1) The sequencer system according to claim 1, comprising a combination of the backplanes that can be connected to each other directly or via a cable. ### Claim 10 (depends on 1) The sequencer system according to claim 1, wherein the data transmission and reception among the units are performed in a fixed cycle. ### Claim 11 (depends on 1) The sequencer system according to claim 1, wherein the units include a network unit connected to a remote unit via a network cable, and the network unit transfers the fixed-cycle clock signal via the network cable. ### Claim 12 (depends on 1) The sequencer system according to claim 1, wherein the units include a network unit connected to a network via a network cable, and the network unit transfers the fixed-cycle clock signal to another sequencer system connected to the network, via the network cable. ### Claim 13 A control method of a sequencer system including a plurality of units, a backplane on which the units are mounted, and a bus communication line for data transmission and reception among the units, wherein the control method comprises: a step of generating a fixed-cycle clock signal having an arbitrary cycle; a step of transferring the fixed-cycle clock signal to the units via the backplane, through an electric signal line provided separately from the bus communication line; a step of generating an interrupt signal corresponding to the fixed-cycle clock signal in the unit; and a step of using the interrupt signal to synchronize control timings of the units.