# US 2013/0252384 A1 · Trench forming method, metal wiring forming method, and method of manufacturing thin film transistor array panel

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- Number: US 2013/0252384 A1
- Document ID: US20130252384A1
- Status: Published application
- Kind: A1
- Application number: 13/556,396
- Filed: 2012-07-24
- Published: 2013-09-26
- Earliest claimed: 2012-03-22
- Assignees: Samsung Display Co., Ltd.
- Inventors: Yong-Hwan RYU; Dae Ho KIM; Hong Sick PARK; Shin Il CHOI
- Web page: https://patentgrep.com/patent/US20130252384A1

## CPC

- H10P 50/73: {using masks for insulating materials}
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 86/0212: {comprising manufacture, treatment or coating of substrates}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- H10P 50/283: {by chemical means}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 50/694: {characterised by their behaviour during the process, e.g. soluble masks or redeposited masks}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 52/403: {of conductive or resistive materials}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a thin film transistor array panel includes: forming a first insulating layer on a substrate; forming an amorphous carbon layer on the first insulating layer; forming a second insulating layer on the amorphous carbon layer; forming an opening in the amorphous carbon layer by patterning the second insulating layer and the amorphous carbon layer; and forming a trench in the first insulating layer by etching the first insulating layer, the etching the first insulating layer using the amorphous carbon layer including the opening as a mask.

## Claims

### Claim 1

A method of forming a thin film transistor array panel, the method comprising:
providing a first insulating layer on a substrate;
providing an amorphous carbon layer on the first insulating layer;
providing a second insulating layer on the amorphous carbon layer;
providing an opening in the amorphous carbon layer, by patterning the second insulating layer and the amorphous carbon layer; and
providing a trench in the first insulating layer, by etching the first insulating layer, the etching the first insulating layer using the amorphous carbon layer comprising the opening as a mask.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
the first insulating layer comprises at least one of SiN, SiO, SiC, SiOC, or SiON.

### Claim 3 (depends on 1)

The method of claim 1, wherein:
the second insulating layer comprises at least one of SiN, SiO, or SiON.

### Claim 4 (depends on 1)

The method of claim 1, wherein:
the providing the opening comprises:
providing a photosensitive film on the second insulating layer, and exposing and developing the photosensitive film, to pattern the photosensitive film;
etching the second insulating layer by using the patterned photosensitive film as a mask;
etching the amorphous carbon layer by using the second insulating layer as a mask, to form the opening; and
removing the photosensitive film.

### Claim 5 (depends on 4)

The method of claim 4, wherein:
in the etching the second insulating layer of the providing the opening and in the etching the first insulating layer of the providing the trench,
the second insulating layer and the first insulating layer are etched by using a first primary etching gas, the first primary etching gas comprising fluorine.

### Claim 6 (depends on 5)

The method of claim 5, wherein:
the first primary etching gas comprises at least one of SF6, NF3, CF4, CHF3, CH2F2, C3F8, C4F8, C4F6, or C5F8.

### Claim 7 (depends on 4)

The method of claim 4, wherein:
in the etching the amorphous carbon layer of the providing the opening,
the amorphous carbon layer is etched by using a second primary etching gas, the second primary etching gas comprising oxygen.

### Claim 8 (depends on 7)

The method of claim 7, wherein:
in the etching the amorphous carbon layer,
the amorphous carbon layer is etched by further using an assistant etching gas, and
the assistant etching gas comprises at least one of hydrogen bromide or argon.

### Claim 9 (depends on 1)

The method of claim 1, wherein:
in the providing the amorphous carbon layer,
the amorphous carbon layer is formed by using a gas, the gas comprising carbon and hydrogen, and
the gas comprising carbon and hydrogen comprises at least one of C2H4, C3H6, or C4H8.

### Claim 10 (depends on 9)

The method of claim 9, wherein:
in the providing the amorphous carbon layer,
the amorphous carbon layer is formed by further using an assistant gas, and
the assistant gas comprises at least one of helium or argon.

### Claim 11 (depends on 10)

The method of claim 10, wherein:
the providing the amorphous carbon layer comprises a chemical vapor deposition process.

### Claim 12 (depends on 11)

The method of claim 11, wherein:
the providing the amorphous carbon layer is performed at a temperature of about 50° Celsius to about 500° Celsius.

### Claim 13

A method of forming a thin film transistor array panel, the method comprising:
providing a first insulating layer on a substrate;
providing an amorphous carbon layer on the first insulating layer;
providing a second insulating layer on the amorphous carbon layer;
patterning the second insulating layer and the amorphous carbon layer, to form an opening in the amorphous carbon layer;
etching the first insulating layer by using the amorphous carbon layer comprising the opening as a mask, to form a trench in the first insulating layer;
removing the amorphous carbon layer;
providing a metal layer on the substrate; and
polishing the metal layer through a chemical mechanical polishing process, to form a metal wiring in the trench.

### Claim 14 (depends on 13)

The method of claim 13, wherein:
the metal wiring comprises copper.

### Claim 15 (depends on 14)

The method of claim 14, wherein:
the first insulating layer comprises one of SiN, SiO, SiC, SiOC, or SiON, and
the second insulating layer comprises at least one of SiN, SiO, or SiON.

### Claim 16 (depends on 14)

The method of claim 14, wherein:
the providing the opening comprises:
providing a photosensitive film on the second insulating layer, and exposing and developing the photosensitive film, to pattern the photosensitive film;
etching the second insulating layer by using the patterned photosensitive film as a mask;
etching the amorphous carbon layer by using the second insulating layer as a mask, to form the opening; and
removing the photosensitive film.

### Claim 17 (depends on 16)

The method of claim 16, wherein:
in the etching the second insulating layer of the providing the opening and in the etching the first insulating layer of the providing the trench,
the second insulating layer and the first insulating layer are etched by using a first primary etching gas, the first primary etching gas comprising fluorine, and
in the etching of the amorphous carbon layer,
the amorphous carbon layer is etched by using a second primary etching gas and an assistant etching gas,
the second primary etching gas comprising oxygen, and the assistant etching gas comprising at least one of hydrogen bromide or argon.

### Claim 18 (depends on 14)

The method of claim 14, wherein:
the providing the amorphous carbon layer comprises a chemical vapor deposition process,
the chemical vapor deposition process uses a gas, the gas comprising carbon and hydrogen, and
the gas comprising carbon and hydrogen comprises at least one of C2H4, C3H6, or C4H8.

### Claim 19

A method of manufacturing a thin film transistor array panel, the method comprising:
providing a first insulating layer on a substrate;
providing an amorphous carbon layer on the first insulating layer;
providing a second insulating layer on the amorphous carbon layer;
patterning the second insulating layer and the amorphous carbon layer to form an opening in the amorphous carbon layer;
etching the first insulating layer by using the amorphous carbon layer comprising the opening as a mask, to form a trench in the first insulating layer;
removing the amorphous carbon layer;
providing a metal layer on the substrate;
polishing the metal layer through a chemical mechanical polishing process, to form a gate electrode in the trench;
providing a gate insulating film on the gate electrode;
providing a semiconductor layer on the gate insulating film;
providing a source electrode and a drain electrode on the semiconductor layer, the source electrode and the drain electrode spaced apart from each other;
providing a passivation film on the source electrode and the drain electrode;
providing a contact hole in the passivation film, the contact hole exposing a portion of the drain electrode; and
providing a pixel electrode on the passivation film, the pixel electrode connected to the drain electrode through the contact hole.

### Claim 20 (depends on 19)

The method of claim 19, wherein:
the metal wiring comprises copper,
the first insulating layer comprises at least one of SiN, SiO, SiC, SiOC, or SiON, and
the second insulating layer comprises at least one of SiN, SiO, or SiON.