# US 2013/0240959 A1 · Semiconductor device and method of fabricating the same

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- Number: US 2013/0240959 A1
- Document ID: US20130240959A1
- Status: Published application
- Kind: A1
- Application number: 13/716,402
- Filed: 2012-12-17
- Published: 2013-09-19
- Earliest claimed: 2012-03-15
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Mongsup LEE; Yoonho SON; Woogwan SHIM; Chan Min LEE; Inseak HWANG
- Web page: https://patentgrep.com/patent/US20130240959A1

## CPC

- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/482: {Bit lines}
- H10B 12/485: {Bit line contacts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device may include a substrate including an active pattern delimited by a device isolation pattern, a gate electrode crossing the active pattern, a first impurity region and a second impurity region in the active pattern on both sides of the gate electrode, a bit line crossing the gate electrode, a first contact electrically connecting the first impurity region with the bit line, and a first nitride pattern on a lower side surface of the first contact. A width of the first contact measured perpendicular to an extending direction of the bit line may be substantially equal to that of the bit line.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate including an active pattern delimited by a device isolation pattern;
a gate electrode crossing the active pattern;
a first impurity region and a second impurity region in the active pattern on both sides of the gate electrode;
a bit line crossing the gate electrode;
a first contact electrically connecting the first impurity region with the bit line, the first contact as measured perpendicular to an extending direction of the bit line having a substantially equal width to that of the bit line; and
a first nitride pattern on a lower side surface of the first contact.

### Claim 2 (depends on 1)

The device of claim 1, wherein a portion of the first impurity region and a portion of the device isolation pattern adjacent thereto are recessed to define a recess region, the recess region having a bottom surface lower than a top surface of the substrate.

### Claim 3 (depends on 2)

The device of claim 2, wherein the first contact includes a portion partially filling the recess region, and the first nitride pattern fills a remaining space of the recess region that is not occupied by the first contact.

### Claim 4 (depends on 1)

The device of claim 1, further comprising:
at least one second contact electrically connected to the second impurity region,
wherein the at least one second contact is electrically isolated from the first contact and the first impurity region by the first nitride pattern.

### Claim 5 (depends on 4)

The device of claim 4,
wherein the at least one second contact is a plurality of second contacts, and the device further includes,
an interlayer insulating pattern on the bit line to electrically separate the plurality of second contacts from each other, and
a second nitride pattern on the bit line.

### Claim 6 (depends on 1)

The device of claim 1, further comprising:
an etch stop pattern between the bit line and the substrate.

### Claim 7 (depends on 1)

The device of claim 1, wherein the first impurity region includes a first recess having a first depth from an upper surface of the substrate, the second impurity region includes a second recess having a second depth from an upper surface of the substrate, and the first depth is greater than the second depth.

### Claim at position 8

-16. (canceled)

### Claim 17

A semiconductor device comprising:
a first impurity region on one side of a gate electrode and a second impurity region on another side of the gate electrode;
a bit line crossing the gate electrode;
a first contact electrically connecting the first impurity region with the bit line;
a first nitride pattern on a lower side surface of the first contact; and
at least one second contact electrically connected to the second impurity region, the at least one second contact being electrically isolated from the first contact and the first impurity region by the first nitride pattern.

### Claim 18 (depends on 17)

The device of claim 17,
wherein the at least one second contact is a plurality of second contacts, and the device further includes,
an interlayer insulating pattern on the bit line to electrically separate the plurality of second contacts from each other; and
a second nitride pattern on the bit line.

### Claim 19 (depends on 17)

The device of claim 17, further comprising:
a substrate including an active pattern delimited by a device isolation pattern, wherein the gate electrode crosses the active pattern.

### Claim 20 (depends on 19)

The device of claim 19, wherein the first impurity region includes a first recess having a first depth from an upper surface of the substrate, the second impurity region includes a second recess having a second depth from an upper surface of the substrate, and the first depth is greater than the second depth.

### Claim 21 (depends on 19)

The device of claim 19, further comprising:
an etch stop pattern between the bit line and the substrate.