# US 2013/0240884 A1 · Detection of environmental conditions in a semiconductor chip

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- Number: US 2013/0240884 A1
- Document ID: US20130240884A1
- Status: Published application
- Kind: A1
- Application number: 13/729,145
- Filed: 2012-12-28
- Published: 2013-09-19
- Earliest claimed: 2012-03-16
- Assignees: Intel Mobile Communications GmbH
- Inventors: Hans-Joachim Barth; Horst Baumeister; Peter Baumgartner; Philipp Riess; Jesenka Veledar Krueger
- Web page: https://patentgrep.com/patent/US20130240884A1

## CPC

- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A capacitive sensor and measurement circuitry is described that may be able to reproducibly measure miniscule capacitances and variations thereof. The capacitance may vary depending upon local environmental conditions such as mechanical stress (e.g., warpage or shear stress), mechanical pressure, temperature, and/or humidity. It may be desirable to provide a capacitor integrated into a semiconductor chip that is sufficiently small and sensitive to accurately measure conditions expected to be experienced by a semiconductor chip.

## Claims

### Claim 1

A circuit, comprising:
a first transistor having a gate, and further having a current path controlled by the gate of the first transistor and coupled between a first input node and a first node of a capacitor;
a second transistor having a gate, and further having a current path controlled by the gate of the second transistor and coupled between a second input node and the first node of the capacitor;
a third transistor having a gate, and further having a current path controlled by the gate of the third transistor and coupled between a third input node and a second node of the capacitor; and
a fourth transistor having a gate, and further having a current path controlled by the gate of the fourth transistor and coupled between a fourth input node and the second node of the capacitor,
wherein the first and second transistors are either all n-type transistors or all p-type transistors and the third and fourth transistors are either all n-type transistors or all p-type transistors.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein each of the first, second, third, and fourth transistors comprises an NMOS transistor.

### Claim 3 (depends on 1)

The circuit of claim 1, further comprising a signal generator configured to generate a first periodic signal and a second periodic signal, and to supply the gates of the first and third transistors with the first periodic signal and the second and fourth transistors with the second periodic signal, wherein the first and second periodic signals are out of phase with each other by 180 degrees.

### Claim 4 (depends on 3)

The circuit of claim 3, wherein the first and second periodic signals are sinusoidal signals.

### Claim 5 (depends on 3)

The circuit of claim 3, further comprising a direct current (DC) voltage generator configured to apply a first DC voltage across the first and second input nodes and a second DC voltage across the third and fourth nodes.

### Claim 6 (depends on 5)

The circuit of claim 5, wherein the DC voltage generator is further configured to apply, over time, the following four permutations of the first and second DC voltages, in no particular order:
a first permutation in which the first DC voltage is +X volts while the second DC voltage is +X volts;
a second permutation in which the first DC voltage is +X volts while the second DC voltage is −X volts;
a third permutation in which the first DC voltage is −X volts while the second DC voltage is −X volts; and
a fourth permutation in which the first DC voltage is −X volts while the second DC voltage is +X volts,
wherein X is a positive value.

### Claim 7 (depends on 6)

The circuit of claim 6, further comprising:
at least one current measurement device configured to measure currents through the first, second, third, and fourth DC input nodes while the four permutations of the first and second DC voltages are applied; and
a controller configured to determine a value based on a combination of the measured currents.

### Claim 8 (depends on 1)

The circuit of claim 1, wherein the first, second, third, and fourth transistors are all n-type transistors.

### Claim 9 (depends on 1)

The circuit of claim 1, wherein the first, second, third, and fourth transistors are all p-type transistors.

### Claim 10

A method, comprising:
applying a first periodic signal to a first node of a circuit and a second periodic signal to a second node of the circuit, wherein the first and second periodic signals are out of phase with each other by 180 degrees, and wherein a capacitor is coupled to the circuit;
while the first and second periodic signals are being applied, applying a first DC voltage across third and fourth nodes of the circuit and a second DC voltage across fifth and sixth nodes of the circuit;
measuring currents through the third, fourth, fifth, and sixth nodes while the first and second DC voltages are being applied; and
determining, based on the measured currents, a value proportional to a capacitance of the capacitor.

### Claim 11 (depends on 10)

The method of claim 10, wherein said applying the first and second DC voltages comprises applying, over time, the following four permutations of the first and second DC voltages, in no particular order:
a first permutation in which the first DC voltage is +X volts while the second DC voltage is +X volts;
a second permutation in which the first DC voltage is +X volts while the second DC voltage is −X volts;
a third permutation in which the first DC voltage is −X volts while the second DC voltage is −X volts; and
a fourth permutation in which the first DC voltage is −X volts while the second DC voltage is +X volts,
wherein X is a positive value.

### Claim 12 (depends on 11)

The method of claim 11, wherein said measuring comprises measuring the currents during each of the four permutations, and wherein said determining comprises:
for each of the four permutations, summing the currents measured during the respective permutation, to result in a first summed current for the first permutation, a second summed current for the second permutation, a third summed current for the third permutation, and a fourth summed current for the fourth permutation; and
determining a value proportional to the capacitance of the capacitor based on a combination of the first, second, third, and fourth summed currents.

### Claim 13 (depends on 12)

The method of claim 12, wherein the combination comprises the first summed current minus the second summed current plus the third summed current minus the fourth summed current.

### Claim 14 (depends on 10)

The method of claim 10, wherein the circuit comprises first, second, third, and fourth transistors, the first node is coupled to a gate of the first transistor and a gate of the third transistor, the second node is coupled to a gate of the second transistor and a gate of the fourth transistor, and the capacitor has a first electrode coupled to a node between current paths of the first and second transistors and a second electrode coupled to a node between current paths of the third and fourth transistors.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first, second, third, and fourth transistors are either all n-type transistors or all p-type transistors.

### Claim 16

A semiconductor chip comprising:
a substrate;
a plurality of layers of material disposed on the substrate;
an active area of the semiconductor chip within which a plurality of circuit elements are disposed in at least some of the layers; and
a capacitor disposed in a keep-out area of the semiconductor chip and electrically coupled to at least one of the circuit elements.

### Claim 17 (depends on 16)

The semiconductor chip of claim 16, wherein the capacitor has a capacitance of less than 50 atto-Farads.

### Claim 18 (depends on 16)

The semiconductor chip of claim 16, wherein the capacitor is disposed in one or more of the layers.

### Claim 19 (depends on 16)

The semiconductor chip of claim 16, wherein the circuit elements comprise a controller configured to determine a value based on a capacitance of the capacitor.

### Claim 20 (depends on 19)

The semiconductor chip of claim 19, wherein the circuit elements further comprise a memory coupled to the controller, wherein the controller is configured to store a history of values of the determined value in the memory.

### Claim 21 (depends on 19)

The semiconductor chip of claim 19, wherein the controller is further configured to generate an early warning signal based on the determined value.

### Claim 22 (depends on 16)

The semiconductor chip of claim 16, further comprising a crackstop structure, wherein the capacitor is disposed between an edge of the semiconductor chip and the crackstop structure.

### Claim 23 (depends on 16)

The semiconductor chip of claim 16, further comprising a crackstop structure and a seal ring disposed around the active area, wherein the capacitor is disposed between an inner side of the seal ring and the crackstop structure.

### Claim 24 (depends on 16)

The semiconductor chip of claim 16, further comprising a pair of seal rings disposed around the active area, wherein the capacitor is disposed between the pair of seal rings.

### Claim 25 (depends on 16)

The semiconductor chip of claim 16, further comprising a seal ring disposed around the active area, wherein the capacitor is disposed between an outer side of the seal ring and an edge of the chip.

### Claim 26 (depends on 16)

The semiconductor chip of claim 16, wherein the capacitor comprises a plurality of electrodes spatially distributed such that the capacitor has a plurality of capacitances at different locations in the capacitor, and wherein the at least one of the circuit elements is configured to determine, for each of the plurality of capacitances, a value based on the respective capacitance.

### Claim 27

A semiconductor chip comprising:
a substrate;
a plurality of layers of material disposed on the substrate;
an active area of the semiconductor chip within which a plurality of circuit elements are disposed in at least some of the layers;
a first seal ring disposed in at least some of the layers and surrounding the active area; and
a capacitor disposed between an outer side of the seal ring and an edge of the semiconductor chip, wherein the capacitor is electrically coupled to at least one of the circuit elements.

### Claim 28 (depends on 27)

The semiconductor chip of claim 27, further comprising a second seal ring disposed in at least some of the layers and surrounding the first seal ring, wherein the capacitor is disposed between the first and second seal rings.

### Claim 29

A semiconductor chip comprising:
a substrate;
a plurality of layers of material disposed on the substrate;
a capacitor disposed in one or more of the layers and having a capacitance of less than 50 atto-Farads (aF);
a circuit electrically coupled to the capacitor and configured to determine a value based on a capacitance of the capacitor to an accuracy of 5 aF or less, and to generate a signal based on the determined value.

### Claim 30 (depends on 29)

The semiconductor chip of claim 29, wherein the capacitor is disposed in a keep-out area of the semiconductor chip and the circuit is disposed in an active area of the chip.

### Claim 31 (depends on 29)

The semiconductor chip of claim 29, further comprising a crackstop structure, wherein the capacitor is disposed between the crackstop structure and an edge of the semiconductor chip.

### Claim 32 (depends on 29)

The semiconductor chip of claim 29, further comprising a crackstop structure and a seal ring, wherein the capacitor is disposed between the crackstop structure and the seal ring.