# US 2013/0240802 A1 · Oxide for semiconductor layer of thin-film transistor, sputtering target, and thin-film transistor

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- Number: US 2013/0240802 A1
- Document ID: US20130240802A1
- Status: Published application
- Kind: A1
- Application number: 13/989,948
- Filed: 2011-11-28
- Published: 2013-09-19
- Earliest claimed: 2010-11-26
- Assignees: Samsung Display Co., Ltd.; Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
- Inventors: Aya Miki; Shinya Morita; Toshihiro Kugimiya; Satoshi Yasuno; Jae Woo Park; Je Hun Lee; Byung Du Ahn
- Web page: https://patentgrep.com/patent/US20130240802A1

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- C23C 14/086: {of zinc, germanium, cadmium, indium, tin, thallium or bismuth}
- C23C 14/3407: {Cathode assembly for sputtering apparatus, e.g. Target}
- C23C 14/3464: {using more than one target (C23C14/56 takes precedence)}
- C23C 14/3492: {Variation of parameters during sputtering}
- C23C 14/548: {Controlling the composition}
- C23C 14/5806: {Thermal treatment}
- C23C 14/5873: {Removal of material}
- H10D 30/6756: {Amorphous oxide semiconductors}
- H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering
- H10P 14/3426: {Oxides}
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

This oxide for a semiconductor layer of a thin-film transistor contains Zn, Sn and In, and at least one type of element (X group element) selected from an X group comprising Si, Hf, Ga, Al, Ni, Ge, Ta, W and Nb. The present invention enables a thin-film transistor oxide that achieves high mobility and has excellent stress resistance (negligible threshold voltage shift before and after applying stress) to be provided.

## Claims

### Claim 1

An oxide
comprising
Zn, Sn and In; and
at least one element X selected from the group consisting of Si, Hf, Ga, Al, Ni, Ge, Ta, and Nb.

### Claim 2 (depends on 1)

The oxide according to claim 1, wherein a content in atomic % of Zn, Sn, and In is [Zn], [Sn], and [In] respectively, and [Zn], [Sn], and [In] satisfy expressions (1) to (3):
[In]/([In]+[Zn]+[Sn])≧−0.53×[Zn]/([Zn]+[Sn])+0.36 (1)
[In]/([In]+[Zn]+[Sn])≧2.28×[Zn]/([Zn]+[Sn])−2.01 (2)
[In]/([In]+[Zn]+[Sn])≦1.1×[Zn]/([Zn]+[Sn])−0.32 (3).

### Claim 3 (depends on 1)

The oxide according to claim 1, wherein a content in atomic % of Zn, Sn, In, and X is [Zn], [Sn], [In], and [X] respectively, a ratio of a content in atomic % of each element X to ([Zn]+[Sn]+[In]+[X]) is represented by {X}, and expression (4) is satisfied:
[−89×<Zn>+74]×[In]/([In]+[Zn]+[Sn])+25×<Zn>−6.5−75×{Si}−120×{Hf}−6.5×{Ga}−123×{Al}−15×{Ni}−244×{Ge}−80×{Ta}−160×{Nb}≧5 (4)
wherein
<Zn>=[Zn]/([Zn]+[Sn]),
{Si}=[Si]/([Zn]+[Sn]+[In]+[X]),
{Hf}=[Hf]/([Zn]+[Sn]+[In]+[X]),
{Ga}=[Ga]/([Zn]+[Sn]+[In]+[X]),
{Al}=[Al]/([Zn]+[Sn]+[In]+[X]),
{Ni}=[Ni]/([Zn]+[Sn]+[In]+[X]),
{Ge}=[Ge]/([Zn]+[Sn]+[In]+[X]),
{Ta}=[Ta]/([Zn]+[Sn]+[In]+[X]), and
{Nb}=[Nb]/([Zn]+[Sn]+[In]+[X]).

### Claim 4 (depends on 2)

The oxide according to claim 2, wherein a content in atomic % of Zn, Sn, In, and X is [Zn], [Sn], [In], and [X] respectively, a ratio of a content in atomic % of each element X to ([Zn]+[Sn]+[In]+[X]) is represented by {X}, and expression (4) is satisfied:
[−89×<Zn>+74]×[In]/([In]+[Zn]+[Sn])+25×<Zn>−6.5−75×{Si}−120×{Hf}−6.5×{Ga}−123×{Al}−15×{Ni}−244×{Ge}−80×{Ta}−160×{Nb}≧5 (4)
wherein
<Zn>=[Zn]/([Zn]+[Sn]),
{Si}=[Si]/([Zn]+[Sn]+[In]+[X]),
{Hf}=[Hf]/([Zn]+[Sn]+[In]+[X]),
{Ga}=[Ga]/([Zn]+[Sn]+[In]+[X]),
{Al}=[Al]/([Zn]+[Sn]+[In]+[X]),
{Ni}=[Ni]/([Zn]+[Sn]+[In]+[X]),
{Ge}=[Ge]/([Zn]+[Sn]+[In]+[X]),
{Ta}=[Ta]/([Zn]+[Sn]+[In]+[X]), and
{Nb}=[Nb]/([Zn]+[Sn]+[In]+[X]).

### Claim 5 (depends on 1)

The oxide according to claim 1, wherein a content in atomic % of Zn, Sn, In, and X is [Zn], [Sn], [In], and [X] respectively, and [Zn], [Sn], [In], and [X] satisfy expression (5):
0.0001≦[X]/([Zn]+[Sn]+[In]+[X]) (5).

### Claim 6 (depends on 1)

A thin-film transistor comprising the oxide according to claim 1 as a semiconductor layer of the thin-film transistor.

### Claim 7 (depends on 6)

The thin-film transistor according to claim 6, wherein a density of the semiconductor layer is 5.8 g/cm3 or higher.

### Claim 8 (depends on 1)

A sputtering target suitable for forming the oxide according to claim 1, wherein
the sputtering target comprises Zn, Sn and In; and at least one element X selected from the group consisting of Si, Hf, Ga, Al, Ni, Ge, Ta, and Nb, and
a content in atomic % of Zn, Sn, and In in the sputtering target is [Zn], [Sn], and [In] respectively, and [Zn], [Sn], and [In] satisfy expressions (1) to (3):
[In]/([In]+[Zn]+[Sn])≧−0.53×[Zn]/([Zn]+[Sn])+0.36 (1)
[In]/([In]+[Zn]+[Sn])≧2.28×[Zn]/([Zn]+[Sn])−2.01 (2)
[In]/([In]+[Zn]+[Sn])≦1.1×[Zn]/([Zn]+[Sn])−0.32 (3).

### Claim 9 (depends on 8)

The sputtering target according to claim 8, wherein a content in atomic % of Zn, Sn, In, and X in the sputtering target is [Zn], [Sn], [In], and [X] respectively, a ratio of a content in atomic % of each element X to ([Zn]+[Sn]+[In]+[X]) is represented by {X}, and expression (4) is satisfied:
[−89×<Zn>+74]×[In]/([In]+[Zn]+[Sn])+25×<Zn>−6.5−75×{Si}−120×{Hf}−6.5×{Ga}−123×{Al}−15×{Ni}−244×{Ge}−80×{Ta}−160×{Nb}≧5 (4)
wherein,
<Zn>=[Zn]/([Zn]+[Sn]),
{Si}=[Si]/([Zn]+[Sn]+[In]+[X]),
{Hf}=[Hf]/([Zn]+[Sn]+[In]+[X]),
{Ga}=[Ga]/([Zn]+[Sn]+[In]+[X]),
{Al}=[Al]/([Zn]+[Sn]+[In]+[X]),
{Ni}=[Ni]/([Zn]+[Sn]+[In]+[X]),
{Ge}=[Ge]/([Zn]+[Sn]+[In]+[X]),
{Ta}=[Ta]/([Zn]+[Sn]+[In]+[X]), and
{Nb}=[Nb]/([Zn]+[Sn]+[In]+[X]).

### Claim 10 (depends on 8)

The sputtering target according to claim 8, wherein a content in atomic % of Zn, Sn, In, and X in the sputtering target is [Zn], [Sn], [In], and [X] respectively, and [Zn], [Sn], [In], and [X] satisfy expression (5):
0.0001≦[X]/([Zn]+[Sn]+[In]+[X]) (5).

### Claim 11 (depends on 2)

A thin-film transistor comprising the oxide according to claim 2 as a semiconductor layer of the thin-film transistor.

### Claim 12 (depends on 3)

A thin-film transistor comprising the oxide according to claim 3 as a semiconductor layer of the thin-film transistor.

### Claim 13 (depends on 4)

A thin-film transistor comprising the oxide according to claim 4 as a semiconductor layer of the thin-film transistor.

### Claim 14 (depends on 5)

A thin-film transistor comprising the oxide according to claim 5 as a semiconductor layer of the thin-film transistor.

### Claim 15 (depends on 11)

The thin-film transistor according to claim 11, wherein a density of the semiconductor layer is 5.8 g/cm3 or higher.

### Claim 16 (depends on 12)

The thin-film transistor according to claim 12, wherein a density of the semiconductor layer is 5.8 g/cm3 or higher.

### Claim 17 (depends on 13)

The thin-film transistor according to claim 13, wherein a density of the semiconductor layer is 5.8 g/cm3 or higher.

### Claim 18 (depends on 14)

The thin-film transistor according to claim 14, wherein a density of the semiconductor layer is 5.8 g/cm3 or higher.