# US 2013/0240366 A1 · Plated terminations

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- Number: US 2013/0240366 A1
- Document ID: US20130240366A1
- Status: Published application
- Kind: A1
- Application number: 13/832,476
- Filed: 2013-03-15
- Published: 2013-09-19
- Earliest claimed: 2002-04-15
- Assignees: AVX Corporation
- Applicants: Avx Corporation
- Inventors: Andrew P. Ritter; Robert Heistand, II; John L. Galvagni; Sriram Dattaguru
- Web page: https://patentgrep.com/patent/US20130240366A1

## CPC

- H01G 4/30: Stacked capacitors (H01G4/33 takes precedence)
- C23C 18/1651: {Two or more layers only obtained by electroless plating}
- C23C 18/1653: {Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating}
- C23C 18/32: Coating with nickel, cobalt or mixtures thereof with phosphorus or boron (C23C18/50 takes precedence)
- C23C 18/38: Coating with copper
- C23C 18/48: Coating with alloys
- C23C 28/021: {including at least one metal alloy layer}
- C23C 28/023: {only coatings of metal elements only}
- C25D 3/56: of alloys
- C25D 5/02: Electroplating of selected surface areas
- C25D 5/34: Pretreatment of metallic surfaces to be electroplated
- C25D 7/00: Electroplating characterised by the article coated
- H01C 1/14: Terminals or tapping points specially adapted for resistors; Arrangements of terminals or tapping points on resistors
- H01C 7/008: {Thermistors (H01C7/02 - H01C7/06 take precedence)}
- H01C 7/10: voltage responsive, i.e. varistors
- H01C 17/28: adapted for applying terminals
- H01F 41/04: for manufacturing coils {(coils for transformer or inductances H01F27/28)}
- H01G 4/005: Electrodes
- H01G 4/008: Selection of materials
- H01G 4/012: Form of non-self-supporting electrodes
- H01G 4/06: Solid dielectrics
- H01G 4/12: Ceramic dielectrics {(H01G4/085 takes precedence)}
- H01G 4/228: Terminals
- H01G 4/232: electrically connecting two or more layers of a stacked or rolled capacitor
- H05K 3/02: in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K 3/403: {Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof (H05K3/4092 takes precedence)}
- H05K 2201/09709: Staggered pads, lands or terminals; Parallel conductors in different planes
- Y10T 29/42: Piezoelectric device making
- Y10T 29/43: Electric condenser making
- Y10T 29/435: Solid dielectric type
- Y10T 29/49002: Electrical device making
- Y10T 29/49099: Coating resistive material on a base
- Y10T 29/49101: Applying terminal
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- C25D: PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- H01C: RESISTORS
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations.

## Claims

### Claim at position 1

1-50. (canceled)

### Claim 51

A method of forming plated terminations on a multi-layer electronic component using a self-determining process, comprising the steps of:
providing electrode layers, and providing dielectric layers which are respectively interleaved with said electrode layers and which otherwise form an insulative substrate;
exposing selected portions of said electrode layers; and
electrolessly plating termination material on the exposed portions of said electrode layers using said exposed portions of said electrode layers as nucleation points and guides for the termination material.

### Claim 52 (depends on 51)

The method of claim 51, wherein the step of electrolessly plating is followed by an electrochemical process.

### Claim 53 (depends on 51)

The method of claim 51, wherein the step of electrolessly plating includes plating termination material on the exposed portions of said electrode layers until the exposed portions of selected of said electrode layers are connected, while otherwise spaced on said insulative substrate.

### Claim 54 (depends on 53)

The method of claim 53, wherein the electrolessly plating step comprises submersing the multi-layer electronic component in an electroless copper plating solution to form a copper termination layer.

### Claim 55 (depends on 54)

The method of claim 54, further comprising the step of covering the copper termination layer with a resistive layer.

### Claim 56 (depends on 55)

The method of claim 55, further comprising the step of plating the resistive layer with a conductive layer.

### Claim 57 (depends on 51)

The method of claim 51, further comprising the steps of:
providing anchor tabs respectively interleaved at selected locations between the dielectric layers; and
exposing portions of said anchor tabs at selected edges of the dielectric layers;
whereby the exposed portions of said anchor tabs function as additional nucleation points and guides for the termination material.

### Claim 58

A method of forming plated terminations on a multi-layer electronic component using a self-determining process, comprising the steps of:
providing electrode layers, and providing dielectric layers which are respectively interleaved with said electrode layers and which otherwise form an insulative substrate;
exposing selected portions of said electrode layers; and
plating termination material on the exposed portions of said electrode layers using said exposed portions of said electrode layers as nucleation points and guides for the termination material;
wherein said plating termination material step comprises one of either electrochemical deposition or electrolessly plating.

### Claim 59 (depends on 58)

A method as in claim 58, wherein said plating termination material step comprises electrolessly plating.

### Claim 60 (depends on 59)

A method as in claim 59, wherein said electrolessly plating comprises depositing a first layer by electrolessly plating.

### Claim 61 (depends on 60)

A method as in claim 60, wherein said electrolessly plating further comprises depositing a second layer by electrolessly plating.

### Claim 62 (depends on 61)

A method as in claim 61, wherein said first layer and said second layer comprise different materials.

### Claim 63 (depends on 61)

A method as in claim 61, wherein said first layer and said second layer comprise metals.

### Claim 64 (depends on 63)

A method as in claim 63, wherein said first layer and said second layer comprise different metals.

### Claim 65 (depends on 59)

A method as in claim 59, wherein said electrolessly plating further includes covering the first layer with resistor-polymeric material before depositing the second layer.

### Claim 66 (depends on 59)

A method as in claim 59, further comprising the steps of:
providing anchor tabs respectively interleaved at selected locations between the dielectric layers; and
exposing portions of said anchor tabs at selected edges of the dielectric layers;
whereby the exposed portions of said anchor tabs function as additional nucleation points and guides for the termination material.

### Claim 67 (depends on 58)

A method as in claim 58, wherein said plating termination material step comprises electrolessly plating a first metal layer and then repeated electrolessly plating a second metal layer of other metal.

### Claim 68 (depends on 59)

A method as in claim 59, wherein the step of electrolessly plating includes plating termination material on the exposed portions of said electrode layers until the exposed portions of selected of said electrode layers are connected, while otherwise spaced on said insulative substrate.

### Claim 69 (depends on 60)

A method as in claim 60, wherein the step of depositing a first layer comprises submersing the multi-layer electronic component in an electroless copper plating solution to form a copper termination layer.

### Claim 70 (depends on 69)

A method as in claim 69, further comprising the step of covering the copper termination layer with a resistive layer.

### Claim 71 (depends on 70)

A method as in claim 70, further comprising the step of plating the resistive layer with a conductive layer.

### Claim 72

A method of forming plated terminations on a multi-layer electronic component using a self-determining process, comprising the steps of:
providing electrode layers, and providing dielectric layers which are respectively interleaved with said electrode layers and which otherwise form an insulative substrate;
exposing selected portions of said electrode layers; and
electrolessly plating termination material on the exposed portions of said electrode layers using said exposed portions of said electrode layers as nucleation points and guides for the termination material;
wherein said electrolessly plating termination material step comprises electrolessly plating a first metal layer and then repeated electrolessly plating a second metal layer of other metal.

### Claim 73 (depends on 72)

A method as in claim 72, wherein said electrolessly plating further includes covering the first layer with resistor-polymeric material before plating the second layer.

### Claim 74 (depends on 72)

A method as in claim 72, wherein the step of electrolessly plating includes plating termination material on the exposed portions of said electrode layers until the exposed portions of selected of said electrode layers are connected, while otherwise spaced on said insulative substrate.

### Claim 75 (depends on 72)

A method as in claim 72, further comprising the steps of:
providing anchor tabs respectively interleaved at selected locations between the dielectric layers; and
exposing portions of said anchor tabs at selected edges of the dielectric layers;
whereby the exposed portions of said anchor tabs function as additional nucleation points and guides for the termination material.