# US 2013/0239591 A1 · Thermal electric cooler and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0239591 A1 - Document ID: US20130239591A1 - Status: Published application - Kind: A1 - Application number: 13/422,990 - Filed: 2012-03-16 - Published: 2013-09-19 - Earliest claimed: 2012-03-16 - Assignees: Raytheon Company - Inventors: Robert R. Clarkson - Web page: https://patentgrep.com/patent/US20130239591A1 ## CPC - F25B 21/02: using Peltier effect; using Nernst-Ettinghausen effect - H10N 10/17: characterised by the structure or configuration of the cell or thermocouple forming the device - H10W 40/28: comprising Peltier coolers - F25B: REFRIGERATION MACHINES, PLANTS OR SYSTEMS; COMBINED HEATING AND REFRIGERATION SYSTEMS; HEAT PUMP SYSTEMS - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract According to an embodiment of the disclosure, a thermal electric cooler is provided that includes a plurality of segments and a plurality of couplers. The segments are coupled in series to form a ladder-configuration string of P-channel chips and N-channel chips. Each segment comprises at least two substrings coupled in parallel. Each substring comprises at least one of the chips. Each of the couplers is configured to couple one of the P-channel chips to one of the N-channel chips. ## Claims ### Claim 1 A thermal electric cooler, comprising: a plurality of segments coupled in series to form a ladder-configuration string of P-channel chips and N-channel chips, wherein each segment comprises at least two substrings coupled in parallel, and wherein each substring comprises at least one of the chips; and a plurality of couplers, wherein each of the couplers is configured to couple one of the P-channel chips to one of the N-channel chips. ### Claim 2 (depends on 1) The thermal electric cooler of claim 1, further comprising a top substrate and a bottom substrate, wherein the segments are coupled between the top substrate and the bottom substrate. ### Claim 3 (depends on 1) The thermal electric cooler of claim 1, further comprising: a first pair of connectors configured to couple a first drive wire to a first one of the segments in the ladder-configuration string; and a second pair of connectors configured to couple a second drive wire to a last one of the segments in the ladder-configuration string. ### Claim 4 (depends on 3) The thermal electric cooler of claim 3, wherein the first drive wire is configured to provide a first signal from a thermal electric cooler controller to the first segment and the second drive wire is configured to provide a second signal from the thermal electric cooler controller to the last segment. ### Claim 5 (depends on 1) The thermal electric cooler of claim 1, further comprising a plurality of shorting bars, wherein each of the shorting bars is configured to couple two of the P-channel chips and two of the N-channel chips to each other. ### Claim 6 (depends on 1) The thermal electric cooler of claim 1, further comprising a plurality of test points, wherein each of the sub strings comprises one of the test points. ### Claim 7 (depends on 6) The thermal electric cooler of claim 6, further comprising a top substrate and a bottom substrate having a periphery, wherein the segments are coupled between the top substrate and the bottom substrate, and wherein the test points are located at the periphery of the bottom substrate. ### Claim 8 (depends on 1) The thermal electric cooler of claim 1, wherein each of the P-channel chips comprises a p-type semiconductor and each of the N-channel chips comprises an n-type semiconductor. ### Claim 9 A thermal electric cooler, comprising: a top substrate; a bottom substrate; a plurality of P-channel chips and a plurality of N-channel chips coupled between the top substrate and the bottom substrate in rows and columns, wherein each of the columns comprises an alternating pattern of the P-channel chips and the N-channel chips and each of the rows comprises an alternating pattern of pairs of the P-channel chips and pairs of the N-channel chips; and a plurality of couplers, wherein each of the couplers is configured to couple one of the P-channel chips to one of the N-channel chips. ### Claim 10 (depends on 9) The thermal electric cooler of claim 9, further comprising a plurality of segments coupled in series to form a ladder-configuration string of the P-channel chips and the N-channel chips, wherein each segment comprises at least two substrings coupled in parallel, and wherein each substring comprises at least one of the chips. ### Claim 11 (depends on 10) The thermal electric cooler of claim 10, further comprising: a first pair of connectors configured to couple a first drive wire to a first one of the segments in the ladder-configuration string; and a second pair of connectors configured to couple a second drive wire to a last one of the segments in the ladder-configuration string. ### Claim 12 (depends on 11) The thermal electric cooler of claim 11, wherein the first drive wire is configured to provide a first signal from a thermal electric cooler controller to the first segment and the second drive wire is configured to provide a second signal from the thermal electric cooler controller to the last segment. ### Claim 13 (depends on 12) The thermal electric cooler of claim 12, wherein the first signal and the second signal cause one of the top substrate and the bottom substrate to provide cooling. ### Claim 14 (depends on 10) The thermal electric cooler of claim 10, further comprising a plurality of test points, wherein each of the substrings comprises one of the test points. ### Claim 15 (depends on 14) The thermal electric cooler of claim 14, wherein the bottom substrate has a periphery, and wherein the test points are located at the periphery of the bottom substrate. ### Claim 16 (depends on 9) The thermal electric cooler of claim 9, further comprising a plurality of shorting bars, wherein each of the shorting bars is configured to couple two of the P-channel chips and two of the N-channel chips to each other. ### Claim 17 (depends on 9) The thermal electric cooler of claim 9, wherein each of the P-channel chips comprises a p-type semiconductor and each of the N-channel chips comprises an n-type semiconductor. ### Claim 18 A method comprising: coupling at least two substrings in parallel to form each of a plurality of segments; and coupling the segments in series to form a ladder-configuration string of P-channel chips and N-channel chips for a thermal electric cooler, wherein each substring comprises at least one of the chips. ### Claim 19 (depends on 18) The method of claim 18, further comprising coupling a plurality of the chips in series to form each of the substrings. ### Claim 20 (depends on 18) The method of claim 18, wherein each of the substrings comprises a single chip, and wherein each segment comprises one of: two P-channel chips and two N-channel chips.