# US 2013/0239409 A1 · Method of manufacturing lead frame and semiconductor package using the lead frame

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- Number: US 2013/0239409 A1
- Document ID: US20130239409A1
- Status: Published application
- Kind: A1
- Application number: 13/875,331
- Filed: 2013-05-02
- Published: 2013-09-19
- Earliest claimed: 2010-06-17
- Assignees: Ambit Microsystems (Zhongshan) Ltd.
- Applicants: Ambit Microsystems (Zhongshan) Ltd.
- Inventors: WANG-LAI YANG
- Web page: https://patentgrep.com/patent/US20130239409A1

## CPC

- H01R 43/00: Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors (of trolley lines B60M1/28)
- H10W 70/421: {Shapes or dispositions}
- H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)}
- H10W 90/00: Package configurations
- H10W 90/811: {Multiple chips on leadframes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/354: {comprising polymers}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/732: {between stacked chips}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- Y10T 29/49204: Contact or terminal manufacturing
- H01R: ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A method of manufacturing a lead frame includes, firstly, forming a metal plate which has a frame portion, a pad portion for mounting semiconductor elements, and lead portions. After that, the lead portions are etched to form a support end, a connecting terminal and a jointing end of each lead portion. Then a receiving portion for receiving the semiconductor elements is formed, wherein the receiving portion is collectively defined by the connecting terminals, the support ends and the pad portion. After that, step portions are formed on the lead portions and the pad portion by half-etching. A method of manufacturing a semiconductor package which includes the lead frame is also provided.

## Claims

### Claim 1

A method of manufacturing a lead frame, comprising:
forming a metal plate to have a structure comprising a frame portion, a pad portion at a center of the frame portion for mounting semiconductor elements, and a plurality of lead portions peripherally extending from the frame portion towards the pad portions;
etching each of the plurality of lead portions to form a support end, a connecting terminal and a jointing end jointing the frame portion with the connecting terminal, the connecting terminal positioned between the jointing end and the support end;
forming a receiving portion for receiving the semiconductor elements, the receiving portion collectively defined by the connecting terminals, the support ends and the pad portion; and
forming a plurality of step portions on the lead portions and the pad portion by half-etching.

### Claim 2 (depends on 1)

The method of claim 1, wherein the lead frame comprises a plurality of support bars connecting the pad portion to corners of the frame portion, and one side of the frame portion, one side of the pad portion and one side of the plurality of support bars collectively form a first surface.

### Claim 3 (depends on 2)

The method of claim 2, wherein the support end of each lead portion, the jointing end of each lead portion and the frame portion are configured on the first surface, the connecting terminal of each lead portion has a top surface protruding from the first surface, and the connecting terminals of the plurality of lead portions surround the pad portion.

### Claim 4 (depends on 1)

The method of claim 1, wherein the plurality of lead portions are etched to space with each other with a first gap and to space with the pad portion with a second gap.

### Claim 5

A method of manufacturing a semiconductor package, comprising:
providing a lead frame to have a structure comprising a frame portion, a pad portion at a center of the lead frame, and a plurality of lead portions peripherally extending from the frame portion towards the pad portion;
etching each of the plurality of lead portions to form a support end, a connecting terminal and a jointing end jointing the frame portion with the connecting terminal, the connecting terminal positioned between the jointing end and the support end, a receiving portion cooperatively formed by the connecting terminals, the support ends and the pad portion;
receiving a first chip in the receiving portion;
mechanically attaching a second chip to the first chip;
connecting the second chip to the connecting terminals via a plurality of bonding wires; and
encapsulating the lead frame, the first chip, the second chip and the plurality of bonding wires.