Enhanced debugging for embedded devices

The machine implemented method as in claim, 1 wherein accessing data in volatile memory of a debug target device comprises:

• accessing, through an external debug interface, the hardware integrated debug framework;
• copying, via the hardware integrated debug framework, one or more page tables on one or more processors from the debug target device to the debug host device, through the external debug interface;
• accessing one or more physical memory addresses on the debug target device using virtual memory mappings listed in one or more page tables copied from one or more processors on the debug target device;
• and
• copying, to the debug host device, one or more blocks of memory stored at the one or more physical memory addresses on the debug target device.

A machine implemented method at a debug host device, the method comprising:

• accessing, through an external debug interface on a debug target device, a hardware integrated debug framework of a system on a chip integrated circuit;
• copying, via the hardware integrated debug framework, a page table on one or more processors from the debug target device, to the debug host device, through the external debug interface;
• analyzing the page table entries to determine the subset of page mapped virtual addresses that contain kernel memory allocations;
• accessing, via the debug framework, one or more physical memory addresses containing kernel memory allocations on the debug target device;
• and
• copying, through the debug interface, one or more blocks of memory stored at the one or more physical memory addresses on the debug target device.

A non-transitory machine-readable storage medium having instructions stored therein, which when executed by a machine cause the machine to perform operations, the operations comprising:

• accessing data in the volatile random access system memory of a debug target device via a hardware integrated debug framework;
• accessing data on a nonvolatile random access electrically erasable semiconductor memory device of the debug target device via the hardware integrated debug framework;
• accessing one or more registers of one or more processors on the debug target device;
• and
• creating a debug target system snapshot on a debug host device, the debug target system snapshot comprising at least the system memory data, the nonvolatile memory data, and the data from one or more registers of one or more processors on the debug target device, wherein the debug target device has malfunctioned due to a failure.

A non-transitory machine-readable storage medium having instructions stored therein, which when executed by a machine cause the machine to perform operations, the operations comprising:

• accessing, through an external debug interface, a hardware integrated debug framework;
• copying, via the hardware integrated debug framework, a page table on one or more processors from the debug target device to the debug host device, through the external debug interface;
• analyzing the page table entries to determine the subset of page mapped virtual addresses that contain kernel memory allocations by applying an algorithm to the set of page mapped virtual addresses, the algorithm comprising analyzing the set of page mapped virtual addresses to find a pattern of mappings, the pattern of mappings to indicate the presence of one or more kernel memory allocations.
• accessing, via the debug framework, one or more physical memory addresses containing kernel memory allocations on the debug target device;
• and
• copying, through the debug interface, one or more blocks of memory stored at the one or more physical memory addresses on the debug target device.

A debugging system for embedded devices, the system comprising:

• a debug host device comprising one or more processors, a main system memory, and a nonvolatile storage device;
• a hardware debug device coupled with the debug host device, the hardware debug device to provide a debug interface between a debug host device and one or more debug target devices;
• a debug target device comprising a system on a chip integrated circuit, volatile DRAM memory, and nonvolatile electrically erasable semiconductor memory, wherein the system on a chip integrated circuit comprises one or more processors and a hardware integrated debug framework, the hardware integrated debug framework to allow the hardware debug device and debug host device to control the one or more processors of the system on a chip integrated circuit after the debug target device malfunctions due to an operating system level failure;
• and
• a debug console, attached to the debug host device, to monitor debug output from the debug target device.