Processor to Execute Shift Right Merge Instructions
AssigneeIntel Corporation
InventorsJulien Sebot, William W. Macy, JR., Eric L. Debes, Huy V. Nguyen
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Abstract
Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
Claims1
A processor comprising:
- a plurality of registers to store 128-bit operands;
- a decoder to decode a single instruction multiple data (SIMD) instruction, the SIMD instruction to indicate a first 128-bit operand having a first set of sixteen byte elements and a second 128-bit operand having a second set of sixteen byte elements, the SIMD instruction to have a 4-bit immediate to specify a number (n) of bytes;
- an execution unit coupled with the decoder and the plurality of registers, the execution unit in response to the SIMD instruction to store a 128-bit result in a destination indicated by the instruction, wherein the result is to include
- the number (n) least significant byte elements of the second operand in the number (n) most significant bytes of the result,
- concatenated with sixteen minus the number (n) most significant byte elements of the first operand in sixteen minus the number (n) least significant bytes of the result.
Dependencies are inferred from the claim text.