Conditional vector mapping in a SIMD processor

A method for performing vector operations in parallel in one step, the method comprising the steps of:

• providing a vector register file including a plurality of vector registers;
• storing a first input vector in said vector register file;
• storing a control vector in said vector register file, wherein said control vector is selected as a source operand of said vector operations;
• selecting a condition flag from a plurality of condition flags for each vector element position in accordance with a condition select field from a vector instruction, said plurality of condition flags are derived from results of executing a prior instruction sequence;
• mapping the elements of said first input vector to the elements of a first output vector, in accordance with a first field of respective element of said control vector;
• and
• storing elements of said first output vector on an element-by-element basis conditionally, if mask bit of respective element of said control vector is interpreted as false and in accordance with respective said selected condition flag,
• wherein said vector operations are performed in parallel in one instruction.

An apparatus for performing vector operations in parallel in accordance with a control vector register and condition flags, the apparatus comprising:

• a vector register file including a plurality of vector registers with a plurality of read data ports and at least one write data port, wherein some of said plurality of vector registers are accessed in parallel and at the same time, said control vector register is part of said vector register file;
• a vector condition flag register for storing a plurality of condition flags for each vector element position, each element of said plurality of condition flags defining a true or false condition value, and a condition select logic that selects one of a plurality of condition flags for each vector element position in accordance with a condition select field from a vector instruction;
• a first select logic coupled to said vector register file for mapping elements of a first vector register in accordance with said control vector register;
• and
• an enable logic coupled to output of said first select logic for controlling storing elements of an output vector register in said vector register file on an element-by-element basis in accordance with a user-defined mask bit for each vector element position of said control vector register and output of said condition select logic for each vector element position,
• wherein said vector operations are performed in parallel by one instruction.

A method for performing vector operations in parallel in one step, the method comprising:

• storing a first input vector;
• storing a control vector;
• selecting a condition flag from a plurality of condition flags for each vector element position, said plurality of condition flags are derived from results of executing a prior instruction sequence;
• mapping the elements of said first input vector to the elements of a first output vector, in accordance with a first field of respective element of said control vector;
• and
• storing elements of said first output vector on an element-by-element basis conditionally in accordance with mask bit of respective element of said control vector is interpreted as false and in accordance with respective said selected condition flag, wherein one of said plurality of condition flags for each respective vector element position is defined as always true.