Memory recorder queue biasing preceding high latency operations

A memory system comprising:

• at least one memory device having a plurality of individually accessible ranks;
• a memory controller coupled to the at least one memory device and controlling the scheduling of memory access operations, wherein the memory controller comprises logic that:
• tracks a time remaining before a scheduled time for performing a high priority, high latency operation a first memory rank of the memory system, wherein the memory system comprises a plurality of ranks that are individually accessible by different memory access operations scheduled from a command re-order queue of the memory controller;
• responsive to the time remaining reaching a pre-established early notification time before the schedule time for performing the high priority, high latency operation, biases the re-order queue containing memory access operations targeting the plurality of ranks to prioritize scheduling of any first memory access operations that target the first memory rank;
• schedules the first memory access operations to the first memory rank for early completion relative to other memory access operations in the re-order queue that target other memory ranks;
• and
• performs the high priority, high latency operation at the first memory rank at the scheduled time;
• wherein the biasing of the re-order queue and scheduling of the first memory access operations triggers a faster reduction of first memory access commands remaining within the re-order queue before the high priority, high latency operation is performed at the first memory rank.

A data processing system comprising:

• one or more one processors;
• a memory system in communication with the processor, the memory system comprising:
• at least one memory device having a plurality of individually accessible ranks;
• and a memory controller coupled to the at least one memory device and controlling the scheduling of memory access operations, wherein the memory controller comprises logic that:
• tracks a time remaining before a scheduled time for performing a high priority, high latency operation a first memory rank of the memory system, wherein the memory system comprises a plurality of ranks that are individually accessible by different memory access operations scheduled from a command re-order queue of the memory controller;
• responsive to the time remaining reaching a pre-established early notification time before the schedule time for performing the high priority, high latency operation, biases the re-order queue containing memory access operations targeting the plurality of ranks to prioritize scheduling of any first memory access operations that target the first memory rank;
• schedules the first memory access operations to the first memory rank for early completion relative to other memory access operations in the re-order queue that target other memory ranks;
• and
• performs the high priority, high latency operation at the first memory rank at the scheduled time;
• wherein the biasing of the re-order queue and scheduling of the first memory access operations triggers a faster depletion of first memory access commands remaining within the re-order queue before the high priority, high latency operation is performed at the first memory rank.