Architecture for address mapping of managed non-volatile memory

A method performed by an embedded non-volatile memory device, the method comprising:

• receiving commands from a host controller requesting operations on non-volatile memory;
• storing the commands in a queue of the non-volatile memory device;
• and
• reordering the commands in the queue in response to a trigger event.

A method performed by an embedded non-volatile memory device, the method comprising:

• receiving read commands from a host controller requesting read operations on non-volatile memory;
• storing the read commands in a first queue;
• receiving program commands from the host controller requesting program operations on the non-volatile memory;
• storing the program commands in a second queue;
• receiving erase commands from the host controller requesting erase operations on the non-volatile memory;
• storing the erase commands in a third queue;
• and
• reordering one or more of the read, program, or erase commands in the first, second, or third queues.

A non-volatile memory (NVM) package, comprising:

• an interface configured to receive a block address and a first chip enable signal from a host processor coupled to the interface;
• a plurality of concurrently addressable memory units each containing a plurality of blocks;
• and
• a processor configured to activate, in response to the chip enable signal from the host processor, a first concurrently addressable memory unit using a first internal chip select enable signal, activate a second concurrently addressable memory unit using a second, internal chip select enable signal, map the block address to blocks in the activated first and second concurrently addressable memory units, and execute a sequence of commands for concurrently performing read or write operations on the blocks in the activated first and second currently addressable memory units.

A system comprising:

• a non-volatile memory (NVM) package;
• and
• a host processor configured to provide a block address and a first chip enable signal to the NVM package, wherein the NVM package comprises a plurality of concurrently address memory unit each containing a plurality of blocks and a processor configured to:
• activate, in response to the chip enable signal from the host processor, a first concurrently addressable memory unit using a first internal chip select enable signal,
• activate a second concurrently addressable memory unit using a second, internal chip select enable signal;
• map the block address to blocks in the activated first and second concurrently addressable memory units;
• and
• execute a sequence of commands for concurrently performing read or write operations on the blocks in the activated first and second currently addressable memory units.

A method comprising:

• receiving, by a processor of a non-volatile memory (NVM) package via an interface, a block address and a first chip enable signal from a host processor, wherein the NVM package includes a plurality of concurrently addressable memory units each containing a plurality of blocks;
• activating, by the processor in response to the chip enable signal from the host processor, a first concurrently addressable memory unit of the NVM package using a first internal chip select enable signal;
• activating, by the processor, a second concurrently addressable memory unit of the NVM package using a second, internal chip select enable signal;
• mapping the block address to blocks in the activated first and second concurrently addressable memory units;
• and
• executing a sequence of commands for concurrently performing read or write operations on the blocks in the activated first and second currently addressable memory units.