Reducing power consumption during manufacturing test of an integrated circuit

A non-transitory computer-readable medium, which when executed, enables a computer system to implement a method for reducing power consumption during a manufacturing test of an integrated circuit (IC), the method comprising:

• providing a plurality of domains, each domain associated with a clock phase;
• grouping, based on each domain, a first plurality of scan chains into a first test group;
• grouping, based on each domain, a second plurality of scan chains into a second test group, wherein the grouping of the first test group and of the second test group includes determining which domains can be tested simultaneously;
• and
• performing the manufacturing test of the IC.

A computer system, comprising:

• at least one computing device configured to reduce power consumption during a manufacturing test of an integrated circuit (IC) by:
• providing a plurality of domains, each domain associated with a clock phase;
• grouping, based on each domain, a first plurality of scan chains into a first test group;
• grouping, based on each domain, a second plurality of scan chains into a second test group, wherein the grouping of the first test group and of the second test group includes determining which domains can be tested simultaneously;
• and
• performing the manufacturing test of the IC.