Reference clock re-timing scheme in electronic circuits

A phase detector for generating an error signal representing a phase difference between an output clock and a reference clock, the phase detector comprising:

• a counter to generate a count value representing an integer portion of a number of complete cycles of the output clock measured at each active edge of the reference clock starting from the commencement of operations of the phase detector;
• a fractional count determination circuit to generate an output representing a fractional portion of the number of complete cycles of the output clock measured at each active edge of the reference clock starting from the commencement of operations of the phase detector;
• a first summing block to add the count value and the output to generate a first number;
• and
• a second summing block to compute a difference of the first number and an accumulated value, wherein the accumulated value represents an expected number of complete cycles of the output clock that should be obtained at each active edge of the reference clock when the reference clock and the output clock are in phase lock, wherein the difference is the error signal,
• wherein the counter is read at an active edge of a first re-timed clock to obtain the integer portion if the magnitude of the fractional portion is either less than or equal to a first threshold or greater than or equal to a second threshold, the counter being read at an active edge of a second re-timed clock to obtain the integer portion if the magnitude of the fractional portion is greater than the first threshold and less than the second threshold, wherein the first threshold represents a first fraction of one cycle of the output clock, wherein the second threshold represents a second fraction of one cycle of the output clock;
• wherein each of the first re-timed clock and the second re-timed clock have a same frequency as the reference clock, each of the first re-timed clock and the second re-timed clock being derived from the reference clock.

An all-digital phase locked loop (ADPLL) comprising:

• a phase detector coupled to receive a reference clock and an output clock, the phase detector to generate an error signal representing a phase difference between the reference clock and the output clock;
• a digital filter to perform low-pass filtering of the error signal to generate a filtered signal;
• and
• a digitally controlled oscillator (DCO) to generate the output clock with a frequency based on a magnitude of the filtered signal,
• wherein the phase detector comprises:
• a counter to generate a count value representing an integer portion of a number of complete cycles of the output clock measured at each active edge of the reference clock starting from the commencement of operations of the phase detector;
• a fractional count determination circuit to generate an output representing a fractional portion of the number of complete cycles of the output clock measured at each active edge of the reference clock starting from the commencement of operations of phase detector;
• a first summing block to add the count value and the output to generate a first number;
• and
• a second summing block to compute a difference of the first number and an accumulated value, wherein the accumulated value represents an expected number of complete cycles of the output clock that should be obtained at each active edge of the reference clock when the reference clock and the output clock are in phase lock, wherein the difference is the error signal,
• wherein the counter is read at an active edge of a first re-timed clock to obtain the integer portion if the magnitude of the fractional portion is either less than or equal to a first threshold or greater than or equal to a second threshold, the counter being read at an active edge of a second re-timed clock to obtain the integer portion if the magnitude of the fractional portion is greater than the first threshold and less than the second threshold, wherein the first threshold represents a first fraction of one cycle of the output clock, wherein the second threshold represents a second fraction of one cycle of the output clock;
• wherein each of the first re-timed clock and the second re-timed clock have a same frequency as the reference clock, each of the first re-timed clock and the second re-timed clock being derived from the reference clock.