Linear system coefficient estimating method, linear device column value estimating method, capacitance detecting method, integrated circuit, touch sensor system, and electronic device

A linear system coefficient estimating method, comprising the steps of:

• (A) (a) inputting, on a basis of M code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and each of which has a length N, M inputs Xk (k=1, . . . , M) to each of a first system and a second system each of which has a linear input and output and to each of which the M inputs Xk (k=1, . . . , M) are to be inputted, the first and second systems being represented by
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• and (b) outputting N outputs sFirst=(s11, s12, . . . , s1N)=(F1 (d11, d21, . . . , dM1), F1 (d12, d22, . . . , dM2), . . . , F1 (d1N, d2N, . . . , dMN)) from the first system and N outputs sSecond=(s21, s22, . . . , s2N)=(F2 (d11, d21, . . . , dM1), F2 (d12, d22, . . . , dM2), . . . , F2 (d1N, d2N, . . . , dMN)) from the second system;
• and
• (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a coefficient C1k of the first system which coefficient C1k corresponds to a k1-th input Xk and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a coefficient C2k of the second system which coefficient C2k corresponds to a k2-th input Xk.

A touch sensor system, comprising:

• a sensor panel including (I) a first capacitance column C1i (i=1, . . . , M) formed between M drive lines and a first sense line and (II) a second capacitance column C2i (i=1, . . . , M) formed between the M drive lines and a second sense line;
• and
• an integrated circuit for controlling the sensor panel,
• the integrated circuit including:
• a drive section for (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, the M drive lines in parallel for each of (I) the first capacitance column C1i (i=1, . . . , M) and (II) the second capacitance column C2i (i=1, . . . , M) so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and thus (b) outputting outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column;
• and
• an estimation section for estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line.

A capacitance detecting method, comprising the steps of:

• (A) (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column;
• and
• (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line,
• the step (A) driving, when the analog integrator is reset, the M drive lines at a first voltage represented by a voltage Vref and driving, when the outputs sFirst and sSecond from the first and second capacitance columns are sampled, the M drive lines at (i) a second voltage for an element of +1 in the code sequences, the second voltage being represented by a voltage (Vref+V), and (ii) a third voltage for an element of −1 in the code sequences, the third voltage being represented by a voltage (Vref−V).

A capacitance detecting method, comprising the steps of:

• (A) (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column;
• and
• (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line,
• the step (A), for an element of +1 in the code sequences, driving the drive lines at (i) a first voltage when the analog integrator is reset and (ii) a second voltage when the outputs sFirst and sSecond from the first and second capacitance columns are sampled and, for an element of −1 in the code sequences, driving the drive lines at (i) the second voltage when the analog integrator is reset and (ii) the first voltage when the outputs sFirst and sSecond from the first and second capacitance columns are sampled.

A capacitance detecting method, comprising the steps of:

• (A) (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column;
• and
• (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line,
• the capacitance detecting method further comprising, before the step (A), the step of:
• (C) (a) driving, when the analog integrator is reset and when the outputs sFirst and sSecond from the first and second capacitance columns are sampled, the drive lines at a first voltage so that the outputs sFirst and sSecond from the first and second capacitance columns are outputted to the analog integrator, (b) reading out, from the analog integrator, the outputs sFirst and sSecond from the first and second capacitance columns as first offset outputs and second offset outputs, respectively, and (c) storing the first and second offset outputs in a memory.

An integrated circuit, comprising:

• a drive section for (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column;
• and
• an estimation section for estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line,
• the drive section, for an element of +1 in the code sequences, driving the drive lines at (i) a first voltage when the analog integrator is reset and (ii) a second voltage when the outputs sFirst and sSecond from the first and second capacitance columns are sampled and, for an element of −1 in the code sequences, driving the drive lines at (i) the second voltage when the analog integrator is reset and (ii) the first voltage when the outputs sFirst and sSecond from the first and second capacitance columns are sampled.

An integrated circuit, comprising:

• a drive section for (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column;
• and
• an estimation section for estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line,
• the drive section, before outputting the outputs sFirst and sSecond from the first and second capacitance columns to the analog integrator, (a) driving, when the analog integrator is reset and when the outputs sFirst and sSecond from the first and second capacitance columns are sampled, the drive lines at a first voltage so that the outputs sFirst and sSecond from the first and second capacitance columns are outputted to the analog integrator, (b) reading out, from the analog integrator, the outputs sFirst and sSecond from the first and second capacitance columns as first offset outputs and second offset outputs, respective, and (c) storing the first and second offset outputs in a memory.

A touch sensor system, comprising:

• a sensor panel including (I) a first capacitance column Ci1 (i=1, . . . , M) formed between M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line;
• and
• an integrated circuit for controlling the sensor panel,
• the integrated circuit including:
• a drive section for (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, the M drive lines in parallel for each of (I) the first capacitance column Ci1 (i=1, . . . , M) and (II) the second capacitance column Ci2 (i=1, . . . , M), and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column;
• and
• an estimation section for estimating (a) on a basis of a first inner product operation of the outputs sFirst the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line,
• the drive section, for an element of +1 in the code sequences, driving the drive lines at (i) a first voltage when the analog integrator is reset and (ii) a second voltage when the outputs sFirst and sSecond from the first and second capacitance columns are sampled and, for an element of −1 in the code sequences, driving the drive lines at (i) the second voltage when the analog integrator is reset and (ii) the first voltage when the outputs sFirst and sSecond from the first and second capacitance columns are sampled.

A touch sensor system, comprising:

• a sensor panel including (I) a first capacitance column Ci1 (i=1, . . . , M) formed between M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line;
• and
• an integrated circuit for controlling the sensor panel,
• the integrated circuit including:
• a drive section for (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, the M drive lines in parallel for each of (I) the first capacitance column Ci1 (i=1, . . . , M) and (II) the second capacitance column Ci2 (i=1, . . . , M), and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column;
• and
• an estimation section for estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line,
• the drive section, before outputting the outputs sFirst and sSecond from the first and second capacitance columns to the analog integrator, (a) driving, when the analog integrator is reset and when the outputs sFirst and sSecond from the first and second capacitance columns are sampled, the drive lines at a first voltage so that the outputs sFirst and sSecond from the first and second capacitance columns are outputted to the analog integrator, (b) reading out, from the analog integrator, the outputs sFirst and sSecond from the first and second capacitance columns as first offset outputs and second offset outputs, respective, and (c) storing the first and second offset outputs in a memory.

A capacitance detecting method, comprising the steps of:

• (A) (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column;
• and
• (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line,
• the step (A), to prevent saturation of the analog integrator, switching a gain of the analog integrator in accordance with an absolute value of a sum total of corresponding elements present in the code sequences along a column direction.

A capacitance detecting method, comprising the steps of:

• (A) (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being either +1 or −1 and each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column;
• and
• (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line,
• the step (A), to prevent saturation of the analog integrator, dividing, in accordance with an absolute value of a sum total of corresponding elements present in the code sequences along a column direction, a column of the code sequences into a plurality of columns so as to divide the driving of the M drive lines into a plurality of drivings.

A capacitance detecting method, comprising the steps of:

• (A) (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being +1 or −1 and each of which has a code length N=M, the code sequences di corresponding to respective rows of a 2n-dimensional Hadamard matrix created by Sylvester method, (M=2n) drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the (M=2n) drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the (M=2n) drive lines and a second sense line, so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column;
• and
• (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line,
• the step (A), to prevent saturation of the analog integrator, dividing a first column of the code sequences into a plurality of columns so as to divide a driving for the first column of the code sequences into a plurality of drivings.

A capacitance detecting method, comprising the steps of:

• (A) (a) driving, on a basis of first code sequences di (=di1, di2, . . . , diN, where i=1, . . . , M) which are orthogonal to one another and include elements each being +1 or −1 and each of which has a code length N>M, the first code sequences di corresponding to respective rows of a 2n-dimensional (where M<2n) Hadamard matrix created by Sylvester method, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, so that a voltage +V is applied for an element of +1 in the first code sequences and that a voltage −V is applied for an element of −1 in the first code sequences, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column;
• and
• (B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the first code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the first code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line,
• the step (A) dividing a particular column of the first code sequences into a plurality of columns, the particular column having an absolute value of a sum total of corresponding elements present in the first code sequences along a column direction which absolute value exceeds a threshold Num for saturation of the analog integrator, so as to divide a driving for the particular column into a plurality of drivings.