Multiplexed read-out architecture for cmos image sensors
AssigneeTexas Instruments Incorporated
InventorJose Tejada-Gomez
Life of this patent
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Abstract
This invention targets improvement in CMOS sensors using a multiplexed read-out architecture in which pixels are output at the pixel VN level instead of the line/reference amplifier level. The pixel signal voltage VN and offset voltage VNS are read sequentially, eliminating the differential structure. Interference rejection, usually achieved by a differential signal, is obtained by using a CDS (Correlated Double Sampler) in the same way as in the prior art.
Claims4
-7. (canceled)
An electronic imager having a plurality of rows and columns of pixels comprising:
- a pixel offset line for each column of pixels receiving a pixel offset of a selected row of a corresponding column of pixels;
- a pixel offset capacitor for each column of pixels connected to a corresponding pixel offset line;
- a pixel offset bus;
- a pixel offset transistor for each column of pixels having a source-drain path connected between a corresponding pixel offset line and said pixel offset bus and a gate;
- a pixel signal line for each column of pixels receiving a pixel signal of a selected row of a corresponding column of pixels;
- a pixel signal capacitor for each column of pixels connected to a corresponding pixel signal line;
- a pixel signal bus;
- a pixel signal transistor for each column of pixels having a source-drain path connected between a corresponding pixel signal line and said pixel signal bus and a gate;
- an output buffer having an input and an output;
- a pixel offset output transistor having a source-drain path connected between said pixel offset bus and said input of said output buffer;
- and
- a pixel signal output transistor having a source-drain path connected between said pixel signal bus and said input of said output buffer.
An electronic imager having a plurality of rows and columns of pixels comprising:
- a pixel offset line for each column of pixels receiving a pixel offset of a selected row of a corresponding column of pixels;
- a pixel offset capacitor for each column of pixels connected to a corresponding pixel offset line;
- a column buffer for each column having an input and an output;
- a pixel offset transistor for each column of pixels having a source-drain path connected between a corresponding pixel offset line and said input of said corresponding column buffer and a gate;
- a pixel signal line for each column of pixels receiving a pixel signal of a selected row of a corresponding column of pixels;
- a pixel signal capacitor for each column of pixels connected to a corresponding pixel signal line;
- a pixel signal transistor for each column of pixels having a source-drain path connected between a corresponding pixel signal line and said input of said corresponding column buffer and a gate;
- an output buffer having an input and an output;
- a column output transistor for each column having a source-drain path connected between said output of a corresponding column buffer and said input of said output buffer.
Dependencies are inferred from the claim text.