US 2013/0200152 A1 · LOW-POWER PULSE WIDTH ENCODING SCHEME AND COUNTER-LESS SHIFT REGISTER THAT MAY BE EMPLOYED THEREWITH

Abstract

A method of decoding an encoded signal includes steps of receiving the encoded signal, creating a decoding signal by delaying the encoded signal by a predetermined amount of time Δ, sampling the encoded signal using the decoding signal, and determining a value of each of a plurality of decoded bits represented by the encoded signal based on the sampling. Also, a method of operating a shift register wherein the shift register has an initialization state wherein a first binary symbol is stored in a first position and a second binary symbol different than the first binary symbol is stored in each of one or more intermediate positions and a last position. The method includes determining that the shift register is full responsive to detecting that the first binary symbol has been stored in either one of the intermediate positions or the last position.

Claims34

Dependent claims

A method of decoding an encoded signal, comprising:

receiving the encoded signal;
creating a decoding signal by delaying the encoded signal by a
predetermined amount of time Δ;
sampling the encoded signal using the decoding signal;
and
determining a value of each of a plurality of decoded bits represented by the encoded signal based on the sampling.

3 more elements

A method of operating a shift register having n sequentially arranged

storage positions comprising a first position, a last position and one or more intermediate positions between the first position and the last position, wherein a bit array stored by the shift register will shift by one position each time that at new bit is loaded into the first position, the method comprising:
causing the shift register to be in an initialization state wherein a first binary symbol is stored in the first position and a second binary symbol different than the first binary symbol is stored in each of the one or more intermediate positions and the last position;
and
determining that the shift register is full responsive to detecting that the first binary symbol has been stored in either one of the intermediate positions or the last position.

1 more element

Dependencies are inferred from the claim text.

Low-power pulse width encoding scheme and counter-less shift register that may be employed therewith

Life of this patent

Low-power pulse width encoding scheme and counter-less shift register that may be employed therewith

Life of this patent

Abstract

Claims34