Copper filling of through silicon vias

A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate, wherein the semiconductor integrated circuit device substrate comprises a front surface, a back surface, and the via feature and wherein the via feature comprises an opening in the front surface of the substrate, a sidewall extending from the front surface of the substrate, and a bottom, the method comprising:

• immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition, wherein the through silicon via feature has an entry dimension between 1 micrometers and 100 micrometers, a depth dimension between 20 micrometers and 750 micrometers, and an aspect ratio greater than about 2:1, the deposition composition comprising:
• (a) a source of copper ions;
• (b) an acid selected from among an inorganic acid, organic sulfonic acid, and mixtures thereof;
• (c) an organic disulfide compound;
• (d) a compound selected from the group consisting of a reaction product of benzyl chloride and hydroxyethyl polyethyleneimine, a quaternized dipyridyl compound, and a combination thereof;
• and
• (d) chloride ions;
• and
• supplying electrical current to the electrolytic deposition composition to deposit copper metal onto the bottom and sidewall for bottom-up filling to thereby yield a copper filled via feature.