Back to results
US 2013/0187215 A1Published application
Methods of forming nanoscale floating gate
AssigneeMicron Technology, Inc.
InventorsGurtej S. Sandhu, D.V. Nirmal Ramaswamy
Life of this patent
Estimating the term…
Abstract
A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.
Claims20
A memory cell, comprising:
- a charge storage structure, wherein the charge storage structure comprises:
- a first conductive portion over a tunnel dielectric;
- and
- a second conductive portion comprising at least one of a nanowire, nanotube, or a nanoribbon.
1 more element
A memory cell, comprising:
- a charge storage structure, wherein the charge storage structure comprises:
- a first conductive portion over a tunnel dielectric;
- and
- a second conductive portion comprising at least one of a nanowire, nanotube, and a nanoribbon having a longest dimension extending from the first conductive portion in an approximately perpendicular direction relative to a surface of the tunnel dielectric.
1 more element
A memory cell, comprising:
- a charge storage structure, wherein the charge storage structure comprises:
- a first conductive portion over a tunnel dielectric;
- and
- a second conductive portion comprising a nanorod having a cross section configured to be one of circular, rectangular, polygonal, or elliptical.
1 more element
Dependencies are inferred from the claim text.